Reconfigurable interconnected programmable processors
A plurality of software programmable processors is disclosed. The software programmable processors are controlled by rotating circular buffers. A first processor and a second processor within the plurality of software programmable processors are individually programmable. The first processor within the plurality of software programmable processors is coupled to neighbor processors within the plurality of software programmable processors. The first processor sends and receives data from the neighbor processors. The first processor and the second processor are configured to operate on a common instruction cycle. An output of the first processor from a first instruction cycle is an input to the second processor on a subsequent instruction cycle.
1. An apparatus for processing comprising:
a plurality of software programmable processors controlled by rotating circular buffers wherein:
a first processor and a second processor within the plurality of software programmable processors are individually programmable;
the first processor within the plurality of software programmable processors is coupled to neighbor processors within the plurality of software programmable processors;
the first processor sends and receives data from the neighbor processors;
the first processor and the second processor are configured to operate on a common instruction cycle;
an output of the first processor from a first instruction cycle is an input to the second processor on a subsequent instruction cycle, wherein the subsequent instruction cycle is an immediately subsequent instruction cycle;
the first processor further comprises an arithmetic logic unit controlled by a circular buffer; and
the circular buffer provides for dynamic programming of the arithmetic logic unit.
2. The apparatus of claim 1 wherein the second processor is one of the neighbor processors.
3. The apparatus of claim 1 wherein an input for the arithmetic logic unit comes from one of the neighbor processors.
4. The apparatus of claim 1 wherein an input for the arithmetic logic unit comes from a location beyond the neighbor processors.
5. The apparatus of claim 1 wherein the first processor further comprises an accumulator wherein the arithmetic logic unit provides input to the accumulator.
6. The apparatus of claim 5 wherein output from the accumulator is provided to one or more of the neighbor processors.
7. The apparatus of claim 5 wherein output from the accumulator is provided to a location beyond the neighbor processors.
8. The apparatus of claim 5 wherein output from the accumulator is provided as input to the arithmetic logic unit.
9. The apparatus of claim 1 wherein the circular buffer is statically scheduled.
10. The apparatus of claim 1 wherein circular buffers of the neighbor processors are programmed to a harmonic length of the circular buffer of the first processor.
11. The apparatus of claim 1 wherein the first processor is configured to avoid data collisions by programming of the circular buffer.
12. The apparatus of claim 1 wherein the plurality of software programmable processors comprises a reconfigurable fabric.
13. The apparatus of claim 1 wherein the common instruction cycle is defined by a hum cycle boundary.
14. The apparatus of claim 1 wherein the plurality of software programmable processors comprises a dataflow processor.
15. The apparatus of claim 1 wherein the first processor is placed into a sleep state.
16. The apparatus of claim 15 wherein the first processor is placed into a sleep state based on a sleep instruction in a circular buffer.
17. The apparatus of claim 16 wherein the first processor wakes from a sleep state based on valid data being present.
18. The apparatus of claim 1 wherein the circular buffer contains instructions.
19. The apparatus of claim 1 wherein the circular buffer contains status bits.
20. The apparatus of claim 1 wherein the circular buffer contains control bits.
21. A processor-implemented method for assembling an apparatus for processing comprising:
including a plurality of software programmable processors controlled by rotating circular buffers, wherein:
a first processor and a second processor within the plurality of software programmable processors are individually programmable;
the first processor further comprises an arithmetic logic unit controlled by a circular buffer; and
the circular buffer provides for dynamic programming of the arithmetic logic unit;
coupling the first processor within the plurality of software programmable processors to neighbor processors within the plurality of software programmable processors;
sending and receiving, by the first processor, data from the neighbor processors;
configuring the first processor and the second processor to operate on a common instruction cycle; and
coupling an output of the first processor from a first instruction cycle to an input to the second processor on a subsequent instruction cycle, wherein the subsequent instruction cycle is an immediately subsequent instruction cycle.
22. A computer program product embodied in a non-transitory computer readable medium for implementation of a computation apparatus comprising code for designing a data manipulation architecture including:
a plurality of software programmable processors controlled by rotating circular buffers wherein:
a first processor and a second processor within the plurality of software programmable processors are individually programmable;
the first processor further comprises an arithmetic logic unit controlled by a circular buffer;
the circular buffer provides for dynamic programming of the arithmetic logic unit;
the first processor within the plurality of software programmable processors is coupled to neighbor processors within the plurality of software programmable processors;
the first processor sends and receives data from the neighbor processors;
the first processor and the second processor are configured to operate on a common instruction cycle; and
an output of the first processor from a first instruction cycle is an input to the second processor on a subsequent instruction cycle, wherein the subsequent instruction cycle is an immediately subsequent instruction cycle.