Instruction encoding for system register bit set and clear
View Patent ↗An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a field for designating which of a plurality of privileged architecture registers is to be modified, a field for designating which bit fields within the designated privileged architecture register is to be modified, and a field to designate whether the designated bit fields are to be set or cleared. The instruction encoding allows a single instruction to atomically set or clear bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification.
1. A method for atomically setting or clearing a bit field within a privileged architecture register of a microprocessor without first reading the contents of the privileged architecture register, the method comprising:
providing a privileged instruction which instructs the microprocessor to set or clear the bit field within the privileged architecture register,
the privileged instruction comprising:
a first operand not stored in a register for specifying which one of a plurality of privileged architecture registers contains the bit field to be set or cleared, and
a designator for specifying whether the bit field is to be set or cleared;
when the microprocessor is in privileged mode, decoding the privileged instruction by examining the first operand to determine which one of the plurality of privileged architecture registers contains the bit field without accessing a register containing a bit mask of bits to set or clear in the privileged architecture register, and by examining the designator to determine whether the bit field is to be set or cleared; and
executing the privileged instruction thereby causing the bit field to be atomically set or cleared according to the designator.
2. The method as recited in claim 1 wherein the privileged mode is the
kernel mode of the microprocessor.
3. The method as recited in claim 1 wherein the privileged architecture register comprises a plurality of bit fields including the bit field to be set or cleared.
4. The method as recited in claim 1 wherein the bit field is an interrupt enable field.
5. The method as recited in claim 1 wherein the privileged instruction further comprises:
a second operand for specifying which one of a plurality of bit fields within a specified one of the plurality of privileged architecture registers is to be set or cleared.
6. The method as recited in claim 5 further comprising:
decoding the second operand to determine which one of a plurality of bit fields within the specified one of the plurality of privileged architecture registers is to be set or cleared.
7. A method for atomically setting or clearing a bit field in a privileged architecture register of a microprocessor, comprising:
providing a privileged instruction that instructs the microprocessor to set or clear the bit field, the privileged instruction comprising:
a first operand to specify which one of a plurality of privileged architecture registers contains the bit field, wherein the first operand does not identify a register that holds a bit mask for setting or clearing bits in the field; and
a designator to specify whether to set or clear the bit field;
decoding the privileged instruction when the microprocessor is in a privileged mode by:
examining the first operand to determine which privileged architecture register contains the bit field; and
examining the descriptor to determine whether to set or clear the bit field; and
executing the privileged instruction to atomically set or clear the bit field without first reading the contents of the privileged architecture register.
8. The method as recited in claim 7 wherein the privileged mode is the kernel mode of the microprocessor.
9. The method as recited in claim 7 wherein the privileged architecture register comprises a plurality of bit fields including the bit field to be set or cleared.
10. The method as recited in claim 7 wherein the bit field is an interrupt enable field.
11. The method as recited in claim 7 wherein the privileged instruction further comprises:
a second operand for specifying which one of a plurality of bit fields within a specified one of the plurality of privileged architecture registers is to be set or cleared.
12. The method as recited in claim 11 further comprising:
decoding the second operand to determine which one of a plurality of bit fields within the specified one of the plurality of privileged architecture registers is to be set or cleared.