Compact logic evaluation gates using null convention

1. A logic circuit comprising:

a pair of inputs where the pair of inputs comprise a null convention logic true input and a null convention logic complement input, wherein the null convention logic true input and the null convention logic complement input have values of “0, 0”to indicate a null condition;

a gate, coupled to the pair of inputs, comprised of a plurality of transistors where:

the plurality of transistors provide for logical signal capture;

the plurality of transistors include a pair of cross-coupled inverters;

the plurality of transistors include a first pull-down device with a transistor-gate node coupled to the null convention logic true input;

the plurality of transistors include a second pull-down device with a transistor-gate node coupled to the null convention logic complement input;

a “1”on the null convention logic true input causes a first side of the pair of cross-coupled inverters to go to a “0”state;

a “1”on the null convention logic complement input causes a second side of the pair of cross-coupled inverters to go to a “0”state; and

a completion circuit, coupled to the pair of inputs and the first side and the second side of the pair of cross-coupled inverters, wherein the completion circuit is responsive to the pair of inputs and the first side and the second side of the pair of cross-coupled inverters.

2. The circuit of claim 1 wherein the pair of cross-coupled inverters retains a value based on a last previous non-null value applied to the pair of inputs.

3. The circuit of claim 1 further comprising a first output of the gate, indicative of a logic state being stored by the pair of cross-coupled inverters.

4. The circuit of claim 3 further comprising a second output of the gate indicative of a logic state being stored by the pair of cross-coupled inverters.

5. The circuit of claim 4 wherein the first output and the second output are inverses of each other.

6. The circuit of claim 1 wherein the null convention logic true input and the null convention logic complement input have valid data values of “0, 1”and “1, 0”indicating a “0”and a “1”, respectively.

7. The circuit of claim 1 wherein the null convention logic true input and the null convention logic complement input have values of “1, 1”which indicate an invalid condition.

8. The circuit of claim 1 wherein the plurality of transistors further comprises a third pull-down device in series with the first pull-down device where the transistor-gate node of the third pull-down device is coupled to an enable signal.

9. The circuit of claim 8 wherein the plurality of transistors further comprises a fourth pull-down device in series with the second pull-down device where the transistor-gate node of the fourth pull-down device is coupled to the enable signal.

10. The circuit of claim 9 wherein the enable signal allows propagation of the null convention logic true input and the null convention logic complement input to the pair of cross-coupled inverters.

11. The circuit of claim 1 wherein the plurality of transistors further comprises a third pull-down device in series with the first pull-down device where the transistor-gate node of the third pull-down device is coupled to a further null convention logic input.

12. The circuit of claim 11 wherein the first pull-down device and the third pull-down device provide for null convention logic calculation.

13. The circuit of claim 1 wherein the plurality of transistors further comprises a fourth pull-down device in series with the second pull-down device where the transistor-gate node of the fourth pull-down device is coupled to a further null convention logic input.

14. The circuit of claim 13 wherein the second pull-down device and the fourth pull-down device provide for null convention logic calculation.

15. The circuit of claim 1 further comprising a read circuit coupled to the pair of cross-coupled inverters which provides a null convention logic true output and a null convention logic complement output.

16. The circuit of claim 15 further comprising a read-done circuit, coupled to the read circuit, which indicates when a read of the pair of cross-coupled inverters is accomplished within a null convention logic environment.

17. A computer-implemented method for using a logic implementation comprising:

obtaining a pair of inputs where the pair of inputs comprises a null convention logic true input and a null convention logic complement input, wherein the null convention logic true input and the null convention logic complement input have values of “0, 0”to indicate a null condition;

applying the null convention logic true input to a null convention logic true input of a null convention logic gate;

applying the null convention logic complement input to a null convention logic complement input of the null convention logic gate;

evaluating outputs for the null convention logic gate based on the null convention logic true input and the null convention logic complement input, wherein the evaluated outputs retain a value based on a last previous non-null value applied to the pair of inputs; and

propagating a completion signal, wherein the completion signal is based on the pair of inputs and the evaluated outputs for the null convention logic gate.

18. A computer-implemented method for logic implementation comprising:

designing a plurality of transistors to form a logic gate wherein:

the logic gate includes a pair of inputs where the pair of inputs comprises a null convention logic true input and a null convention logic complement input, wherein the null convention logic true input and the null convention logic complement input have values of “0, 0”to indicate a null condition;

the logic gate is coupled to the pair of inputs wherein:

the plurality of transistors provides for logical signal capture;

the plurality of transistors includes a pair of cross-coupled inverters;

the plurality of transistors includes a first pull-down device with a transistor-gate node coupled to the null convention logic true input;

the plurality of transistors includes a second pull-down device with a transistor-gate node coupled to the null convention logic complement input;

a “1”on the null convention logic true input causes a first side of the pair of cross-coupled inverters to go to a “0”state;

a “1”on the null convention logic complement input causes a second side of the pair of cross-coupled inverters to go to a “0”state; and

the plurality of transistors includes a completion circuit, coupled to the pair of inputs and the first side and the second side of the pair of cross-coupled inverters, wherein the completion circuit is responsive to the pair of inputs and the first side and the second side of the pair of cross-coupled inverters.

19. A computer system for logic implementation comprising:

a memory which stores instructions;

one or more processors coupled to the memory wherein the one or more processors are configured to:

design a plurality of transistors to form a logic gate wherein:

the logic gate includes a pair of inputs where the pair of inputs comprises a null convention logic true input and a null convention logic complement input, wherein the null convention logic true input and the null convention logic complement input have values of “0, 0”to indicate a null condition;

the logic gate is coupled to the pair of inputs wherein:

the plurality of transistors provides for logical signal capture;

the plurality of transistors includes a pair of cross-coupled inverters;

the plurality of transistors includes a first pull-down device with a transistor-gate node coupled to the null convention logic true input;

the plurality of transistors includes a second pull-down device with a transistor-gate node coupled to the null convention logic complement input;

a “1”on the null convention logic true input causes a first side of the pair of cross-coupled inverters to go to a “0”state;

a “1”on the null convention logic complement input causes a second side of the pair of cross-coupled inverters to go to a “0”state; and

the plurality of transistors includes a completion circuit, coupled to the pair of inputs and the first side and the second side of the pair of cross-coupled inverters, wherein the completion circuit is responsive to the pair of inputs and the first side and the second side of the pair of cross-coupled inverters.

20. The circuit of claim 1 , wherein the completion circuit further comprises an additional pair of cross-coupled inverters having a first side and a second side.

21. The circuit of claim 20 further comprising a read circuit coupled to the pair of cross-coupled inverters which provides a null convention logic true output and a null convention logic complement output.

22. The circuit of claim 21 further comprising a read-done circuit, coupled to the read circuit, which indicates when a read of the pair of cross-coupled inverters is accomplished within a null convention logic environment, wherein the coupling to the read circuit is to the second side of the additional pair of cross-coupled inverters.

23. The circuit of claim 22 wherein the completion circuit further comprises a first, a second, a third, and a fourth NMOS transistor coupled to the first side of the additional pair of cross-coupled inverters.

24. The circuit of claim 23 wherein the completion circuit further comprises a first and a second PMOS transistor coupled to the first side of the additional pair of cross-coupled inverters.