IP Library Granted Patent US 11,481,472
Granted Patent B2
US 11,481,472 · App. 16/943,252 · Granted Oct 25, 2022

Integer matrix multiplication engine using pipelining

Inventor: David John Simpson (San Jose, CA)
G06F17/16
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Quick Facts
Patent No.
US 11,481,472
App. No.
16/943,252
Granted
Oct 25, 2022
Kind
B2
Abstract

Techniques for data manipulation using integer matrix multiplication using pipelining are disclosed. A first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n are obtained for matrix multiplication within a processor. The first and second integer matrices employ a two's complement variable radix point data representation. The first and second integer matrices are distilled into (j×j) submatrices. A first variable radix point format and an initial value for an accumulator register are configured dynamically. A first variable radix point format is configured dynamically for the first integer matrix and a second variable radix point format is configured dynamically for the second integer matrix. Multiply-accumulate operations are executed in a pipelined fashion on the (j×j) submatrices of the first integer matrix and the second integer matrix, where a third variable radix point format is configured for the result.

Claims (33)

1. A processor-implemented method for data manipulation comprising:

obtaining a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation;

distilling the first integer matrix and the second integer matrix into (j×j) submatrices;

configuring dynamically both a variable radix point format and an initial value for an accumulator register; and

executing multiply-accumulate operations in a pipelined architecture on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result.

2. The method of claim 1 further comprising configuring dynamically a first variable radix point format for the first integer matrix and a second variable radix point format for the second integer matrix.

3. The method of claim 2 wherein the first variable radix point format and the second variable radix point format comprise a 16-bit data type.

4. The method of claim 2 wherein the first variable radix point format and the second variable radix point format comprise a 4-bit primitive data type.

5. The method of claim 2 wherein the first variable radix point format and the second variable radix point format comprise an 8-bit primitive data type.

6. The method of claim 1 wherein j is 4.

7. The method of claim 1 wherein j is 8.

8. The method of claim 1 further comprising outputting results of the matrix multiplication to a storage element, wherein the outputting takes an additional (m×k) cycles.

9. The method of claim 1 further comprising presenting a first element from a third matrix and a first element from a fourth matrix to a first multiply-accumulate (MAC) unit after (m×k) cycles.

10. The method of claim 9 wherein a second dimension of the fourth matrix is the same as a second dimension of the second integer matrix.

11. The method of claim 1 wherein the first integer matrix and the second integer matrix comprise subsections of an o-dimensional tensor, wherein o is greater than 2.

12. The method of claim 1 wherein each multiply-accumulate (MAC) unit used for matrix multiplication in the processor is configured to have an accumulator depth of m.

13. The method of claim 1 further comprising pipelining input elements to multiply-accumulate (MAC) units used for matrix multiplication in the processor through two input registers.

14. The method of claim 1 wherein performing N multiply-accumulate (MAC) operations in parallel reduces an amount of time taken to perform the N MAC operations from an order of magnitude of N 3 to an order of magnitude of N 2 .

15. The method of claim 1 further comprising adding one or more idle or no operation (NOP) cycles after completion of a matrix multiply operation before starting a next matrix multiply operation.

16. The method of claim 1 wherein a processor and memory subsystem is allocated as part of one or more clusters within a reconfigurable fabric to implement MAC units.

17. The method of claim 1 wherein input elements of the first matrix are taken from a row of the first matrix.

18. The method of claim 1 wherein input elements of the second matrix are taken from a column of the second matrix.

19. A computer program product embodied in a non-transitory computer readable medium for data manipulation, the computer program product comprising code which causes one or more processors to perform operations of:

obtaining a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation;

distilling the first integer matrix and the second integer matrix into (j×j) submatrices;

configuring dynamically both a variable radix point format and an initial value for an accumulator register; and

executing multiply-accumulate operations in a pipelined architecture on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result.

20. A computer system for data manipulation comprising: a memory which stores instructions;

one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:

obtain a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation;

distill the first integer matrix and the second integer matrix into (j×j) submatrices;

configure dynamically both a variable radix point format and an initial value for an accumulator register; and

execute multiply-accumulate operations in a pipelined architecture on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result.

Assignments (5)
CHANGE OF NAME Recorded May 8, 2024
From: WAVE COMPUTING, INC.
To: MIPS HOLDING, INC.
Reel/Frame 067355/0324 →
RELEASE OF SECURITY INTEREST Recorded Dec 29, 2022
From: CAPITAL FINANCE ADMINISTRATION, LLC, AS ADMINISTRATIVE AGENT
To: MIPS TECH, LLC; WAVE COMPUTING INC.
Reel/Frame 062251/0251 →
SECURITY INTEREST Recorded Jun 14, 2021
From: MIPS TECH, LLC; WAVE COMPUTING, INC.
To: CAPITAL FINANCE ADMINISTRATION, LLC
Reel/Frame 056558/0903 →
RELEASE OF SECURITY INTEREST Recorded Jun 14, 2021
From: WAVE COMPUTING LIQUIDATING TRUST
To: MIPS TECH, INC.; HELLOSOFT, INC.; WAVE COMPUTING (UK) LIMITED; IMAGINATION TECHNOLOGIES, INC.; CAUSTIC GRAPHICS, INC.; MIPS TECH, LLC; WAVE COMPUTING, INC.
Reel/Frame 056589/0606 →
SECURITY INTEREST Recorded Feb 26, 2021
From: WAVE COMPUTING, INC.; MIPS TECH, LLC; MIPS TECH, INC.; HELLOSOFT, INC.; WAVE COMPUTING (UK) LIMITED; IMAGINATION TECHNOLOGIES, INC.; CAUSTIC GRAPHICS, INC.
To: WAVE COMPUTING LIQUIDATING TRUST
Reel/Frame 055429/0532 →
Cited By (1)
US 12,223,011