Translation lookaside buffer
View Patent ↗Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support visualization and multi-threading. Disclosed embodiments pertain to a TLB that includes a content addressable memory (CAM) with variable page size entries and a set associative memory with fixed page size entries. The CAM may include: a first set of logically contiguous entry locations, wherein the first set comprises a plurality of subsets, and each subset comprises logically contiguous entry locations for exclusive use of a corresponding virtual processing element (VPE); and a second set of logically contiguous entry locations, distinct from the first set, where the entry locations in the second set may be shared among available VPEs. The set associative memory may comprise a third set of logically contiguous entry locations shared among the available VPEs distinct from the first and second set of entry locations.
1. A physical Translation Lookaside Buffer (TLB) comprising: a physical content addressable memory, wherein the content addressable memory comprises a first set of entry locations, wherein each entry location in the first set is usable by one or more of a plurality of available virtual processing elements (VPEs), a first group of entries of said entry locations being allocated to a root process associated with a corresponding VPE by mapping, in sequential ascending order, a lowest numbered TLB entry in the first set to a lowest numbered entry index used by the root process to address the TLB entry; and
a physical set associative memory, the set associative memory comprising a second set of entry locations distinct from the first set of entry locations, wherein the second set of entry locations is shared among the available VPEs.
2. The TLB of claim 1 , wherein the TLB is capable of simultaneously looking up TLB lookup requests in the content addressable memory and the set associative memory.
3. The TLB of claim 1 , wherein the first set of entry locations comprises a plurality of subsets, each subset of entry locations comprising:
a first group of entries for the exclusive use of a corresponding root process associated with a VPE corresponding to the subset.
4. The TLB of claim 3 , wherein each subset of entry locations further comprises: a second group of entries, distinct from the first group of entries, for the exclusive use of a guest process running on the VPE corresponding to the subset.
5. The TLB of claim 4 , wherein each subset of entry locations further comprises:
a third group of entries, distinct from the first and second groups, wherein the third group is shared between the root process and the guest process.
6. The TLB of claim 4 , wherein:
the entries in each subset are numbered sequentially;
and the second group of entries is allocated to the guest process by mapping, in sequential descending order, a highest numbered TLB entry in the first subset to a lowest numbered entry index used by the guest process to address the TLB entry.
7. The TLB of claim 5 , wherein: entries in the third group are managed in accordance with a replacement policy associated with the VPE corresponding to the subset.
8. A physical Translation Lookaside Buffer (TLB) comprising:
a physical content addressable memory, wherein the content addressable memory comprises a first set of entry locations, wherein each entry location in the first set is usable by one or more of a plurality of available virtual processing elements (VPEs), and a physical set associative memory, the set associative memory comprising a second set of entry locations distinct from the first set of entry locations, wherein the second set of entry locations is shared among the available VPEs, wherein:
the entries are numbered sequentially,
a first group of entries being allocated to the root process by mapping, in sequential descending order, a highest numbered TLB entry in the entry locations to a lowest numbered entry index used by the root process to address the TLB entry; and
a second group of entries being allocated to the guest process by mapping, in sequential ascending order, a lowest numbered TLB entry in the entry locations to a lowest numbered entry index used by the guest process to address the TLB entry.
9. A processor configurable to support a plurality of available Virtual Processing Elements (VPEs), the processor comprising a Memory Management Unit (MMU), wherein the MMU comprises:
a physical Translation Lookaside Buffer (TLB) comprising:
a physical content addressable memory, wherein the content addressable memory comprises a first set of entry locations, wherein each entry location in the first set is usable by one or more of a plurality of available virtual processing elements (VPEs), a first group of entries being allocated to a root process associated with a corresponding VPE by mapping, in sequential ascending order, a lowest numbered TLB entry in the entry locations to a lowest numbered entry index used by the root process to address the TLB entry; and
a physical set associative memory, the set associative memory comprising a second set of entry locations distinct from the first set of entry locations, wherein the second set of entry locations is shared among the available VPEs.
10. The processor of claim 9 , wherein the TLB is capable of simultaneously looking up TLB lookup requests in the content addressable memory and the set associative memory.
11. The processor of claim 9 , wherein the first set of entry locations comprises a plurality of subsets, each subset of entry locations comprising:
a first group of entries for the exclusive use of a corresponding root process associated with a VPE corresponding to the subset.
12. The processor of claim 11 , wherein each subset of entry locations further comprises: a second group of entries, distinct from the first group of entries, for the exclusive use of a guest process running on the VPE corresponding to the subset.
13. The processor of claim 12 , wherein each subset of entry locations further comprises: a third group of entries, distinct from the first and second groups, wherein the third group is shared between the root process and the guest process.
14. The processor of claim 12 , wherein: the entries in each subset are numbered sequentially;
and
the second group of entries is allocated to the guest process by mapping, in sequential descending order, a highest numbered TLB entry in the first subset to a lowest numbered entry index used by the guest process to address the TLB entry.
15. A processor configurable to support a plurality of available Virtual Processing Elements (VPEs), the processor comprising a Memory Management Unit (MMU), wherein the MMU comprises:
a physical Translation Lookaside Buffer (TLB) comprising:
a physical content addressable memory, wherein the content addressable memory comprises a first set of entry locations, wherein each entry location in the first set is usable by one or more of a plurality of available virtual processing elements (VPEs); and
a physical set associative memory, the set associative memory comprising a second set of entry locations distinct from the first set of entry locations, wherein the second set of entry locations is shared among the available VPEs; the first set of entry locations comprises a plurality of subsets, the entries in each subset being numbered sequentially; a first group of entries is allocated to the root process by mapping, in sequential descending order, a highest numbered TLB entry in a first subset to a lowest numbered entry index used by the root process to address the TLB entry; and a second group of entries is allocated to the guest process by mapping, in sequential ascending order, a lowest numbered TLB entry in the first subset to a lowest numbered entry index used by the guest process to address the TLB entry.
16. The processor of claim 13 , wherein: entries in the third group are managed in accordance with a replacement policy associated with the VPE corresponding to the subset.