Multi-threshold circuitry based on silicon-on-insulator technology
View Patent ↗Multiple threshold voltage circuitry based on silicon-on-insulator (SOI) technology is disclosed which utilizes N-wells and/or P-wells underneath the insulator in SOI FETs. The well under a FET is biased to influence the threshold voltage of the FET. A PFET and an NFET share a common buried P-well or N-well. Various types of logic can be fabricated in silicon-on-insulator (SOI) technology using multiple threshold voltage FETs. Embodiments provide circuits including the advantageous properties of both low-leakage transistors and high-speed transistors.
1. An apparatus for digital evaluation comprising:
a plurality of transistors configured to form a logic gate where the plurality of transistors are formed in a silicon-on-insulator (SOI) semiconductor technology, wherein:
the plurality of transistors include a plurality of PFETs;
the plurality of transistors include a plurality of NFETs;
a first PFET, from the plurality of PFETs, and a first NFET, from the plurality of NFETs, share a first buried well under an insulator in the silicon-on-insulator semiconductor technology;
a second PFET, from the plurality of PFETs, and a second NFET, from the plurality of NFETs, share a second buried well under an insulator in the silicon-on-insulator semiconductor technology; and
a first connection that biases the first buried well and a second connection that biases the second buried well wherein the first buried well is biased so that the first PFET or the first NFET has a low threshold voltage and the second buried well is biased so that the second PFET or the second NFET has a low threshold voltage.
2. The apparatus of claim 1 wherein transistors with the low threshold voltage are used for logical evaluation.
3. The apparatus of claim 1 wherein one of the first PFET or the first NFET has a high threshold voltage.
4. The apparatus of claim 1 wherein one of the second PFET or the second NFET has a high threshold voltage.
5. The apparatus of claim 1 wherein a PFET, from the plurality of PFETs, is in a buried well with an NFET, from the plurality of NFETs, and the PFET forms a header transistor.
6. The apparatus of claim 5 wherein the header transistor has a high threshold voltage as a result of biasing for the buried well.
7. The apparatus of claim 5 wherein the header transistor includes a source connection and a drain connection where the drain connection provides a virtual power supply rail.
8. The apparatus of claim 1 wherein an NFET, from the plurality of NFETs, is in a buried well with a PFET, from the plurality of PFETs, and the NFET forms a footer transistor.
9. The apparatus of claim 8 wherein the footer transistor has a high threshold voltage as a result of biasing for the buried well.
10. The apparatus of claim 9 wherein the footer transistor, with the high threshold voltage, limits current through the logic gate.
11. The apparatus of claim 8 wherein the footer transistor provides a virtual ground rail.
12. The apparatus of claim 1 wherein the logic gate implements a Boolean logic operation where the logic gate is part of a clocked Boolean logic circuit.
13. The apparatus of claim 1 wherein the logic gate implements a null convention logic (NCL) gate.
14. The apparatus of claim 13 further comprising a flash connection for the NCL gate where the NCL gate is a flash NCL gate.
15. The apparatus of claim 1 wherein biasing for the first buried well is changed dynamically.
16. The apparatus of claim 1 wherein biasing for the second buried well is changed dynamically.
17. The apparatus of claim 1 wherein the plurality of transistors includes a high threshold voltage PFET and a low threshold voltage PFET.
18. The apparatus of claim 1 wherein the plurality of transistors include one or more three-dimensional transistors.
19. A computer program product embodied in a non-transitory computer readable medium for implementation of a logical calculation apparatus comprising:
code for designing a plurality of transistors to form a logic gate where the plurality of transistors are formed in a silicon-on-insulator (SOI) semiconductor technology, wherein:
the plurality of transistors include a plurality of PFETs;
the plurality of transistors include a plurality of NFETs;
a first PFET, from the plurality of PFETs, and a first NFET, from the plurality of NFETs, share a first buried well under an insulator in the silicon-on-insulator semiconductor technology;
a second PFET, from the plurality of PFETs, and a second NFET, from the plurality of NFETs, share a second buried well under an insulator in the silicon-on-insulator semiconductor technology; and
a first connection that biases the first buried well and a second connection that biases the second buried well wherein the first buried well is biased so that the first PFET or the first NFET has a low threshold voltage and the second buried well is biased so that the second PFET or the second NFET has a low threshold voltage.
20. A computer system for implementation of a logical calculation apparatus comprising:
a memory which stores instructions;
one or more processors coupled to the memory wherein the one or more processors are configured to:
design a plurality of transistors to form a logic gate where the plurality of transistors are formed in a silicon-on-insulator (SOI) semiconductor technology, wherein:
the plurality of transistors include a plurality of PFETs;
the plurality of transistors include a plurality of NFETs;
a first PFET, from the plurality of PFETs, and a first NFET, from the plurality of NFETs, share a first buried well under an insulator in the silicon-on-insulator semiconductor technology;
a second PFET, from the plurality of PFETs, and a second NFET, from the plurality of NFETs, share a second buried well under an insulator in the silicon-on-insulator semiconductor technology; and
a first connection that biases the first buried well and a second connection that biases the second buried well wherein the first buried well is biased so that the first PFET or the first NFET has a low threshold voltage and the second buried well is biased so that the second PFET or the second NFET has a low threshold voltage.