Decoding instructions that are modified by one or more other instructions
Methods and apparatus are provided for decoding instructions in a computer program wherein the instructions include one or more base instructions that are subject to modification by one or more other instructions. A decoder determines whether a first received instruction was arrived at by a non-incremental change to a program counter (i.e. a jump in the program). If the first instruction was arrived at by a non-incremental change to the program counter the decoder decodes the immediately preceding instruction to determine if the original instruction is a base instruction subject to modification by one or more other instructions. If the preceding instruction indicates that the original instruction is a base instruction an error has occurred and exception handling code is invoked.
1. A method of storing a computer program in a program memory, the computer program comprising a plurality of instructions, the method comprising:
receiving the plurality of instructions at a compiler, the plurality of instructions comprising one or more base instructions and at least one modifier instruction for each base instruction;
analyzing, at the compiler, the plurality of instructions to identify each base instruction and the at least one modifier instruction for each identified base instruction; and
storing each identified base instruction on a same side of a boundary within the program memory as the at least one modifier instruction for that identified base instruction, wherein the storing each identified base instruction on the same side of a boundary within the program memory as the at least one modifier instruction for that identified base instruction comprises reordering the plurality of instructions so that each identified base instruction is stored on the same side of a boundary within the program memory as the at leak one modifier instruction for that identified base instruction.
2. The method of claim 1 , wherein a boundary within the program memory comprises one or more of a beginning of a cache line, an end of a cache line and a memory management unit page.
3. The method of claim 1 , wherein each modifier instruction is a postfix instruction.
4. The method of claim 1 , each modifier instruction is a prefix instruction.
5. The method of claim 1 , wherein storing an identified base instruction on the same side of a boundary within the program memory as the at least one modifier instruction for that base instruction comprises inserting one or more No Operation instructions in the computer program before the identified base instruction or the at least one modifier instruction for the identified base instruction so that the identified base instruction and the at least one modifier instruction for that identified base instruction are stored on the same side of a boundary within the program memory.
6. The method of claim 1 , wherein the plurality of instructions comprises at least two modifier instructions for a base instruction, the method further comprising storing the base instruction on the same side of a boundary of the program memory as the at least two modifier instructions for that base instruction.
7. A device arranged to store a computer program, the computer program comprising a plurality of instructions, the device comprising:
a program memory; and
a processor configured to:
receive the plurality of instructions, the plurality of instructions comprising one or more base instructions and at least one modifier instruction for each base instruction,
analyze the plurality of instructions to identify each base instruction and the at least one modifier instruction for each identified base instruction, and
store each identified base instruction on a same side of a boundary within the program memory as the at least one modifier instruction for that identified base instruction wherein the processor is configured to store each identified base instruction on the same side of a boundary within the program memory as the at least one modifier instruction for that identified base instruction by reordering the plurality of instructions so that each identified instruction is stored on the same side of a boundary within the program memory as the at least one modifier instruction for that identified base instruction.
8. The device of claim 7 , wherein a boundary within the program memory comprises one or more of a beginning of a cache line, an end of a cache line and a memory management unit page.
9. The device of claim 7 , wherein each modifier instruction is a postfix instruction.
10. The device of claim 7 , wherein each modifier instruction is a prefix instruction.
11. The device of claim 7 , wherein the processor is configured to store an identified base instruction on the same side of a boundary within the program memory as the at least one modifier instruction for that identified base instruction by inserting one or more No Operation instructions in the computer program before the identified base instruction or the at least one modifier instruction for the identified base instruction so that the identified base instruction and the at least one modifier instruction for that base instruction are stored on the same side of a boundary within the program memory.
12. The device of claim 7 , wherein the plurality of instructions comprises at least two modifier instructions for a base instruction, and the processor is configured to store that base instruction on the same side of a boundary of the program memory as the at least two modifier instructions for that base instruction.
13. A data processing apparatus arranged to execute a computer program, the data processing apparatus comprising:
a program memory configured to store the computer program, the computer program comprising a plurality of instructions, the plurality of instructions comprising one or more base instructions and at least one modifier instruction for each base instruction, the plurality of instructions stored in the program memory so that each base instruction is stored on a same side of a boundary within the program memory as the at least one modifier instruction for that base instruction;
a program counter configured to identify a first instruction in the program memory;
a fetch unit configured to retrieve the first instruction in the program memory identified by the program counter; and
a decode unit configured to:
receive the first instruction from the fetch unit, and
request an additional instruction from the fetch unit to look for a modifier instruction for the first instruction, the additional instruction being an instruction immediately preceding the first instruction in the program memory or an instruction immediately following the first instruction in the program memory;
wherein the fetch unit is further configured to determine whether the additional instruction is on the same side of a boundary of the program memory as the first instruction, and in response to determining that the additional instruction is not on the same side of the boundary of the program memory, avoid fetching the additional instruction from the program memory.