Restoring a register renaming map
View Patent ↗A technique for restoring a register renaming map is described. In one example, a restore table having a number of storage locations saves a copy of the register renaming map whenever a flow-risk instruction is passed to a re-order buffer. When all storage locations are full, further instructions still pass to the re-order buffer, but a copy of the map is not saved. A storage location subsequently becomes available when its associated flow-risk instruction is executed. A register renaming map state for an unrecorded flow-risk instruction passed to the re-order buffer whilst the storage locations were full is generated and stored in the available location. This is generated using the restore table entry for a previous flow-risk instruction and re-order buffer values for intervening instructions between the previous and unrecorded flow-risk instructions. The restore table can be used to restore the map if an unexpected change in instruction flow occurs.
1. A method of restoring a register renaming map in an out-of-order processor, comprising:
updating a register commit map whenever an instruction is output from a re-order buffer to a commit stage, wherein the register commit map is updated using the re-order buffer values for the mapping between a destination architectural register and a physical register for each instruction output from the re-order buffer;
in response to detecting an unexpected change in instruction flow, marking the instruction in the re-order buffer as requiring restore;
flushing a front end of the processor, including a fetch stage and a decode and renaming stage;
fetching instructions from a correct address;
waiting until the marked instruction is output to the commit stage; and
restoring the register renaming map using the register commit map.
2. A method according to claim 1 , further comprising:
flushing a back end of the processor, including the re-order buffer and the commit stage after restoring the register renaming map.
3. An out-of-order processor, comprising:
a register renaming map;
a re-order buffer; and
a commit stage arranged to receive executed instructions from the re-order buffer, and commit the executed instructions to memory; and
a register commit map arranged to store a mapping between the architectural destination register and the physical register for each instruction input to the commit stage,
wherein the processor is arranged:
in response to detecting an unexpected change in instruction flow, to mark the instruction in the re-order buffer as requiring restore;
to flush a front end of the processor, including a fetch stage and a decode and renaming stage;
to fetch instructions from a correct address;
to wait until the marked instruction is output to the commit stage; and
to restore the register renaming map using the register commit map.