Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor
View Patent ↗A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and a second operand. The microprocessor executes the fork instruction by allocating context for the new thread, copying the first operand to a program counter of the new thread context, copying the second operand to a register of the new thread context, and scheduling the new thread for execution. If no new thread context is free for allocation, the microprocessor raises an exception to the fork instruction. The fork instruction is efficient because it does not copy the parent thread general purpose registers to the new thread. The second operand is typically used as a pointer to a data structure in memory containing initial general purpose register set values for the new thread.
1. A multiprocessing system comprising:
a multithreaded microprocessor having a plurality of logical processor contexts each of which appears to an N-way symmetric multiprocessor (SMP) operating system executing on the multithreaded microprocessor as a multithreaded virtual processing element (VPE),
wherein the SMP operating system manages a simultaneously executing plurality of threads that can be created and destroyed without operating system intervention,
wherein threads can be scheduled in response to external conditions with no interrupt latency, and
wherein each thread context comprises a result register having two read ports and one write port for supporting execution of an instruction that performs exactly two reads, one from a first operand register containing a first operand and one from a second operand register containing a second operand and a single write of the second operand to one destination register in a register set during a single clock cycle.
2. The multiprocessing system of claim 1 , wherein threads scheduled in response to external conditions are system service threads.
3. The multiprocessing system of claim 1 , wherein each thread context comprises a collection of bits in registers that describe the execution state of a thread, ,a program counter (PC) and a per-thread control register.
4. The multiprocessing system of claim 1 , further comprising a processor context, stored in per-processor control registers, associated with each VPE.
5. The multiprocessing system of claim 1 , wherein each VPE comprises a set of per-processor control registers and a status register with a field for specifying a most recently dispatched thread exception raised by an exception signal, and wherein if a VPE issues an instruction to allocate resources for a new thread when free allocatable thread contexts are not available, a value in the exception field indicates a thread overflow condition.
6. A multiprocessing system comprising:
a multithreaded microprocessor having a plurality of logical processor contexts each of which appears to an N-way symmetric multiprocessor (SMP) operating system executing on the multithreaded microprocessor as a multithreaded virtual processing element (VPE),
wherein the SMP operating system manages a simultaneously executing plurality of threads that can be created and destroyed without operating system intervention,
wherein the execution of a single RISC-like instruction in a parent thread allocates resources for a new thread and schedules execution of the new thread, and
wherein each thread context comprises a result register having two read ports and one write port for supporting execution of an instruction that performs exactly two reads, one from a first operand register containing a first operand and one from a second operand register containing a second operand and a single write of the second operand to one destination register in a register set during a single clock cycle.
7. The multiprocessing system of claim 6 , wherein the single RISC-like instruction is issued by the SMP operating system.
8. The multiprocessing system of claim 6 , wherein the single RISC-like instruction is issued by a user level thread.
9. The multiprocessing system of claim 8 , wherein very short code regions of user code are parallelized into multiple threads.
10. The multiprocessing system of claim 6 , wherein the single RISC-like instruction transfers a value to a program counter associated with the new thread and transfers a value from a register in to define a location of a data structure for populating registers of the new thread.
11. The multiprocessing system of claim 6 , wherein the single RISC-like instruction includes an opcode field that indicates the instruction is a SPECIAL3 type instruction within the MIPS ISA and a function field that indicates that the function is a FORK instruction.