Implementation method for fast NCL data path
View Patent ↗An implementation method for a fast Null Convention Logic (NCL) data path includes a pipeline that is assembled from gates of various types of NCL. Self-ready flash NCL gates include a one-shot circuit to reset the gates to a null state and prepare the gates for the next wave of asserted data. In one embodiment, the one-shot circuit creates a flash pulse inside a gate in response to a change of a flash input line and ends the flash pulse in response to the gate output being reset to a null state. Conventional logic can be included in the data path as well.
1. A logical pipeline comprising:
a plurality of gates wherein the gates are comprised of:
a plurality of transistors wherein the plurality of transistors provide for logical evaluation;
a plurality of input lines, each having an asserted state and a null state, connected to one or more of the gates;
a flash input line, having a first state and a second state, connected to one or more of the gates;
an output line, having an asserted output state and a null output state, connected to one or more of the gates; and
a data path formed from the plurality of gates wherein at least one gate includes a one-shot circuit wherein the one-shot circuit has an input attached to the flash input line and the one-shot circuit is used by the at least one gate to set the output line of the gate into the null output state.
2. The logical pipeline of claim 1 wherein the at least one gate with the one-shot circuit comprises a self-ready flash null convention logic gate.
3. The logical pipeline of claim 1 further comprising a registration stage that provides information to the plurality of input lines for at least one of the plurality of gates.
4. The logical pipeline of claim 3 wherein an output of the registration stage is connected to one of the plurality of input lines for one of the plurality of gates, wherein the output of the registration stage has an asserted state and a null state.
5. The logical pipeline of claim 3 further comprising a completion-detection circuit connected to a plurality of output signal lines from the registration stage.
6. The logical pipeline of claim 5 wherein an output from the completion-detection circuit is connected to a previous registration stage.
7. The logical pipeline of claim 6 wherein the previous registration stage resets based on information from the completion-detection circuit.
8. The logical pipeline of claim 7 wherein outputs from the previous registration stage are set to a null state when the previous registration stage resets.
9. The logical pipeline of claim 5 further comprising a flash null generation circuit connected to one or more outputs of the registration stage.
10. The logical pipeline of claim 9 wherein the flash null generation circuit is connected to the flash input line of a self-ready flash NCL gate.
11. The logical pipeline of claim 9 wherein the flash null generation circuit provides a signal that resets one or more gates from the plurality of gates.
12. The logical pipeline of claim 11 wherein outputs from the one or more gates are set into a null state based on signal from the flash null generation circuit.
13. The logical pipeline of claim 1 wherein the data path includes one or more gates which are reset without the use of the one-shot circuit.
14. The logical pipeline of claim 13 wherein the one or more gates which are reset without the use of the one-shot circuit are flash NCL gates.
15. The logical pipeline of claim 13 wherein the one or more gates which are reset without the use of the one-shot circuit are null convention logic gates.
16. The logical pipeline of claim 15 wherein an output from a self-ready flash NCL gate is an input to a standard NCL gate.
17. The logical pipeline of claim 15 wherein an output from a self-ready flash NCL gate is an input to a flash NCL gate.
18. The logical pipeline of claim 1 wherein the one-shot circuit is shared across multiple gates.
19. A computer implemented method for logic implementation comprising:
incorporating a plurality of gates wherein the gates are comprised of:
a plurality of transistors wherein the plurality of transistors provide for logical evaluation;
a plurality of input lines, each having an asserted state and a null state, connected to one or more of the gates;
a flash input line, having a first state and a second state, connected to one or more of the gates;
an output line, having an asserted output state and a null output state, connected to one or more of the gates; and
connecting a data path formed from the plurality of gates wherein at least one gate includes a one-shot circuit wherein the one-shot circuit has an input attached to the flash input line and the one-shot circuit is used by the at least one gate to set the output line of the gate into the null output state.
20. A computer system for logic implementation comprising:
a memory which stores instructions;
one or more processors coupled to the memory wherein the one or more processors are configured to:
include a plurality of gates wherein the gates are comprised of:
a plurality of transistors wherein the plurality of transistors provide for logical evaluation;
a plurality of input lines, each having an asserted state and a null state, connected to one or more of the gates;
a flash input line, having a first state and a second state, connected to one or more of the gates;
an output line, having an asserted output state and a null output state, connected to one or more of the gates; and
connect a data path formed from the plurality of gates wherein at least one gate includes a one-shot circuit wherein the one-shot circuit has an input attached to the flash input line and the one-shot circuit is used by the at least one gate to set the output line of the gate into the null output state.