Hum generation circuitry
View Patent ↗Systems and methods for clock generation and distribution are disclosed. Embodiments include arrangements of synchronization signals implemented using a mesh circuit. The mesh circuit is comprised of a plurality of null convention logic (NCL) gates organized into rings. Each ring shares at least one NCL gate with an adjacent ring. The rings are configured in such a way that each ring in the mesh operates synchronously with the other rings in the mesh.
1. An apparatus for signal generation comprising:
a first ring including a plurality of NCL logic gates wherein:
the first ring includes at least four NCL logic gates comprising a first pipeline wherein the first pipeline feeds back on itself;
the first ring generates a first synchronization signal; and
a second ring including a plurality of NCL logic gates comprising a second pipeline wherein the second pipeline feeds back on itself and wherein:
one NCL logic gate is common between the first ring and the second ring;
the second ring generates a second synchronization signal; and
the first synchronization signal and the second synchronization signal are coordinated based on the one NCL logic gate that is common between the first ring and the second ring.
2. The apparatus of claim 1 further comprising a reset signal coupled to the at least four NCL logic gates that comprise the first ring.
3. The apparatus of claim 2 wherein the reset signal is coupled to the plurality of NCL logic gates that comprise the second ring.
4. The apparatus of claim 1 wherein the first synchronization signal includes a clock edge.
5. The apparatus of claim 1 further comprising an asynchronous circuit where the first synchronization signal is used to coordinate the asynchronous circuit with a second circuit.
6. The apparatus of claim 1 further comprising a synchronous circuit where the first synchronization signal is used to coordinate the synchronous circuit with a second circuit.
7. The apparatus of claim 1 wherein the first synchronization signal and the second synchronization signal are coordinated such that the first synchronization signal and the second synchronization signal generates the same frequency.
8. The apparatus of claim 1 wherein the first synchronization signal and the second synchronization signal are coordinated such that the first synchronization signal and the second synchronization signal maintain a same cycle count.
9. The apparatus of claim 1 further comprising a plurality of other rings wherein:
the other rings comprise a plurality of NCL logic gates;
an NCL logic gate is shared among, up to four rings, among the other rings; and
the other rings have a respective synchronization signal and the respective synchronization signals are coordinated.
10. The apparatus of claim 9 wherein the first ring, the second ring, and the plurality of other rings form a clock coordination signal generation structure.
11. The apparatus of claim 9 wherein the first ring, the second ring, and the plurality of other rings form a clock generation structure.
12. The apparatus of claim 1 wherein the second ring includes at least four NCL logic gates.
13. The apparatus of claim 12 further comprising a reset signal coupled to the plurality of NCL logic gates of the first ring, the plurality of NCL logic gates of the second ring, and the plurality of NCL logic gates that comprise the other rings.
14. The apparatus of claim 1 wherein the first ring comprises 16 NCL logic gates and wherein the second ring comprises 16 NCL logic gates.
15. The apparatus of claim 14 wherein the first ring and the second ring have two data tokens in each.
16. The apparatus of claim 14 wherein the first ring and the second ring have four data tokens in each.
17. A computer-implemented method for logic implementation comprising:
including a plurality of NCL logic gates;
connecting four of the plurality of NCL logic gates to form a first pipeline wherein the first pipeline feeds back on itself wherein the first pipeline generates a first synchronization signal;
connecting four of the plurality of NCL logic gates to form a second pipeline wherein the second pipeline feeds back on itself wherein the second pipeline generates a second synchronization signal; and
connecting at least one NCL logic gate so that it is shared in common between the first pipeline and the second pipeline wherein the first synchronization signal and the second synchronization signal are coordinated based on the at least one NCL logic gate that is shared in common.
18. A computer program product embodied in a non-transitory computer readable medium for logic implementation, the computer program product comprising:
code for including a plurality of NCL logic gates;
code for connecting four of the plurality of NCL logic gates to form a first pipeline wherein the first pipeline feeds back on itself wherein the first pipeline generates a first synchronization signal;
code for connecting four of the plurality of NCL logic gates to form a second pipeline wherein the second pipeline feeds back on itself wherein the second pipeline generates a second synchronization signal; and
code for connecting at least one NCL logic gate so that it is shared in common between the first pipeline and the second pipeline wherein the first synchronization signal and the second synchronization signal are coordinated based on the at least one NCL logic gate that is shared in common.