IP Library Granted Patent US 10,949,328
Granted Patent B2
US 10,949,328 · App. 16/502,110 · Granted Mar 16, 2021

Data flow graph computation using exceptions

Inventors: Keith Mark Evans (San Jose, CA); Stephen Curtis Johnson (Morgan Hill, CA)
Assignee: Wave Computing, Inc.
G06F11/3612G06F8/433G06F11/0709G06F11/0721G06F15/7871
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Quick Facts
Patent No.
US 10,949,328
App. No.
16/502,110
Granted
Mar 16, 2021
Kind
B2
Abstract

Techniques are disclosed for data manipulation within a reconfigurable computing environment for data flow graph computation using exceptions. Processing elements are configured within a reconfigurable fabric to implement a data flow graph. The processing elements are loaded with process agents. Valid data is executed by a first process agent on a first processing element, where the first process agent corresponds to a starting node of the data flow graph. A second processing element detects that an error exception has occurred, where a second process agent is running on the second processing element. A done signal to a third process agent is withheld by the second process agent, where the third process agent is running on a third processing element. The second process agent raises an interrupt request, where the interrupt request is based on the detecting that an error exception has occurred.

Claims (42)

1. A processor-implemented method for data manipulation comprising:

configuring a plurality of processing elements to implement a data flow graph;

loading the plurality of processing elements with a plurality of process agents;

executing valid data by a first process agent on a first processing element from the plurality of processing elements, wherein the first process agent corresponds to a starting node of the data flow graph;

detecting, by a second processing element from the plurality of processing elements, that an error exception has occurred, wherein a second process agent is running on the second processing element;

raising, by the second process agent, an interrupt request, wherein the interrupt request is based on the detecting, by the second processing element from the plurality of processing elements, that the error exception has occurred; and

in response to the interrupt request, withholding a done signal, by the second process agent, to a third process agent, wherein the third process agent is running on a third processing element from the plurality of processing elements.

2. The method of claim 1 wherein execution ceases based on the interrupt request.

3. The method of claim 1 wherein a state of the second process agent is stored based on the interrupt request.

4. The method of claim 1 wherein the third process agent is upstream within the data flow graph from the second process agent.

5. The method of claim 1 wherein the first process agent and the second process agent are the same agent.

6. The method of claim 1 further comprising withholding, by the second process agent, a fire signal from a fourth process agent, wherein the fourth process agent is running on a fourth processing element from the plurality of processing elements.

7. The method of claim 6 wherein the fourth process agent is downstream within the data flow graph from the second process agent.

8. The method of claim 1 further comprising entering, by the second process agent, an error state, wherein the error state is based on the detecting by the second processing element.

9. The method of claim 8 further comprising polling the plurality of processing elements to identify the error state.

10. The method of claim 9 wherein the polling is accomplished by an execution manager.

11. The method of claim 10 wherein the execution manager is part of a host outside of the plurality of processing elements.

12. The method of claim 11 wherein the host is separately clocked from the plurality of processing elements.

13. The method of claim 1 wherein the error exception includes a code debugging error.

14. The method of claim 1 wherein the error exception includes an arithmetic exception.

15. The method of claim 14 wherein the arithmetic exception includes a divide by zero exception.

16. The method of claim 14 wherein the arithmetic exception includes an underflow exception.

17. The method of claim 14 wherein the arithmetic exception includes an overflow exception.

18. The method of claim 1 wherein the error exception includes a signaling error.

19. The method of claim 18 wherein the signaling error includes a direct memory access abort, a buffer overflow, a buffer underflow, excessive saturation, or an excessive re-computation attempt.

20. The method of claim 1 wherein the processing elements comprise a reconfigurable fabric.

21. A computer program product embodied in a non-transitory computer readable medium for data manipulation, the computer program product comprising code which causes one or more processors to perform operations of:

configuring a plurality of processing elements to implement a data flow graph;

loading the plurality of processing elements with a plurality of process agents;

executing valid data by a first process agent on a first processing element from the plurality of processing elements, wherein the first process agent corresponds to a starting node of the data flow graph;

detecting, by a second processing element from the plurality of processing elements, that an error exception has occurred, wherein a second process agent is running on the second processing element;

raising, by the second process agent, an interrupt request, wherein the interrupt request is based on the detecting, by the second processing element from the plurality of processing elements, that the error exception has occurred; and

in response to the interrupt request, withholding a done signal, by the second process agent, to a third process agent, wherein the third process agent is running on a third processing element from the plurality of processing elements.

22. A computer system for data manipulation comprising:

a memory which stores instructions;

one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:

configure a plurality of processing elements to implement a data flow graph;

load the plurality of processing elements with a plurality of process agents;

execute valid data by a first process agent on a first processing element from the plurality of processing elements, wherein the first process agent corresponds to a starting node of the data flow graph;

detect, by a second processing element from the plurality of processing elements, that an error exception has occurred, wherein a second process agent is running on the second processing element;

raise, by the second process agent, an interrupt request, wherein the interrupt request is based on detection, by the second processing element from the plurality of processing elements, that the error exception has occurred; and

in response to the interrupt request, withhold a done signal, by the second process agent, to a third process agent, wherein the third process agent is running on a third processing element from the plurality of processing elements.

Assignments (6)
CHANGE OF NAME Recorded May 8, 2024
From: WAVE COMPUTING, INC.
To: MIPS HOLDING, INC.
Reel/Frame 067355/0324 →
RELEASE OF SECURITY INTEREST Recorded Dec 29, 2022
From: CAPITAL FINANCE ADMINISTRATION, LLC, AS ADMINISTRATIVE AGENT
To: MIPS TECH, LLC; WAVE COMPUTING INC.
Reel/Frame 062251/0251 →
SECURITY INTEREST Recorded Jun 14, 2021
From: MIPS TECH, LLC; WAVE COMPUTING, INC.
To: CAPITAL FINANCE ADMINISTRATION, LLC
Reel/Frame 056558/0903 →
RELEASE OF SECURITY INTEREST Recorded Jun 14, 2021
From: WAVE COMPUTING LIQUIDATING TRUST
To: MIPS TECH, INC.; HELLOSOFT, INC.; WAVE COMPUTING (UK) LIMITED; IMAGINATION TECHNOLOGIES, INC.; CAUSTIC GRAPHICS, INC.; MIPS TECH, LLC; WAVE COMPUTING, INC.
Reel/Frame 056589/0606 →
SECURITY INTEREST Recorded Feb 26, 2021
From: WAVE COMPUTING, INC.; MIPS TECH, LLC; MIPS TECH, INC.; HELLOSOFT, INC.; WAVE COMPUTING (UK) LIMITED; IMAGINATION TECHNOLOGIES, INC.; CAUSTIC GRAPHICS, INC.
To: WAVE COMPUTING LIQUIDATING TRUST
Reel/Frame 055429/0532 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2019
From: EVANS, KEITH MARK; JOHNSON, STEPHEN CURTIS
To: WAVE COMPUTING, INC.
Reel/Frame 050008/0672 →
Continuity (24)
Continuation In Part 16104586 · Aug 17, 2018
Provisional Application 62856490 · Jun 3, 2019
Provisional Application 62850059 · May 20, 2019
Provisional Application 62827333 · Apr 1, 2019
Provisional Application 62802307 · Feb 7, 2019
Provisional Application 62800432 · Feb 2, 2019
Provisional Application 62773486 · Nov 30, 2018
Provisional Application 62694984 · Jul 7, 2018
Provisional Application 62692993 · Jul 2, 2018
Provisional Application 62679046 · Jun 1, 2018
Provisional Application 62679172 · Jun 1, 2018
Provisional Application 62650425 · Mar 30, 2018
Provisional Application 62650758 · Mar 30, 2018
Provisional Application 62637614 · Mar 2, 2018
Provisional Application 62636309 · Feb 28, 2018
Provisional Application 62611600 · Dec 29, 2017
Provisional Application 62611588 · Dec 29, 2017
Provisional Application 62594563 · Dec 5, 2017
Provisional Application 62594582 · Dec 5, 2017
Provisional Application 62579616 · Oct 31, 2017
Provisional Application 62577902 · Oct 27, 2017
Provisional Application 62547769 · Aug 19, 2017
Provisional Application 62857925 · Jun 6, 2019
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