Methods and systems that identify and power up ways for future instructions are provided. A processor includes an n-way set associative cache and an instruction fetch unit. The n-way set associative cache is configured to store instructions. The instruction fetch unit is in communication with the n-way set associative cache and is configured to power up a first way, where a first indication is associated with an instruction and indicates the way where a future instruction is located and where the future instruction is two or more instructions ahead of the current instruction.
1. An apparatus comprising: a processor; an associative cache configured to store a plurality of instructions in a plurality of selectively powered ways; and an instruction fetch unit configured to fetch, for execution by said processor, a current instruction from said associative cache in accordance with an instruction pointer; wherein said processor is configured to identify a way of said associative cache in which a future instruction that is a predetermined plurality of instructions ahead of said current fetched instruction is located, using way information for the future instruction that is associated with said current fetched instruction and retrieved together with said current fetched instruction, and said identified way of said associative cache is selectively powered at a time corresponding to when that said future instruction needs to be fetched by said instruction fetch unit.
2. The apparatus of claim 1 , wherein:
the processor processes instructions in pipelined stages;
the information associated with the fetched instruction is a lookahead indicator;
the lookahead indicator is retrieved at a second stage of said pipeline; and
the way associated with the future instruction is identified using the lookahead indicator at a third stage of said pipeline.
3. The apparatus of claim 2 , wherein the lookahead indicator is stored as a prefix to the first instruction.
4. The apparatus of claim 2 , wherein the lookahead indicator is stored in a way lookahead buffer.
5. The apparatus of claim 1 , further comprising a branch target buffer (BTB) configured to provide a branch indicator that indicates one or more ways of the plurality of ways where an instruction after a branch is located if the branch is taken.
6. The apparatus of claim 5 , wherein the BTB further comprises a next-to-target indicator indicating where a way associated with a next-to-target instruction is located, and wherein the next-to-target indicator is used to power the way associated with the next-to-target instruction.
7. The apparatus of claim 6 , wherein either the lookahead indicator or the next-to-target indicator is used to determine which of the plurality of ways to power based on a BTB prediction.
8. The apparatus of claim 6 , wherein the next-to-target indicator further comprises ways for instructions after the next-to-target instruction.
9. The apparatus of claim 5 , wherein the instruction fetch unit is further configured to use the BTB to power one or more of the plurality of ways.
10. The apparatus of claim 5 , wherein the BTB is further configured to provide a prediction of a result if the branch is taken.
11. The apparatus of claim 5 , wherein the BTB further comprises a next-to-target way lookahead cache configured to provide information for instructions that are two or more instructions ahead of the branch.
12. The apparatus of claim 1 , wherein the associative cache is a 2-, 4-, or 8-way set associative cache.
13. The apparatus of claim 1 , wherein the instructions are stored in the associative cache based on the lower byte of an instruction pointer.
14. A method comprising: fetching, in accordance with an instruction pointer, for execution by a processor, a current instruction from an associative cache configured to store a plurality of instructions in a plurality of selectively powered ways; identifying a way of said associative cache in which a future instruction that is a predetermined plurality of instructions ahead of said current fetched instruction is located, using way information for the future instruction that is associated with said current fetched instruction and retrieved together with said current fetched instruction, and selectively powering said identified way of said associative cache at a time corresponding to when that said future instruction needs to be fetched by said instruction fetch unit.
15. The method of claim 14 , wherein said information is part of a branch target buffer (BTB) entry for said fetched instruction.
16. The method of claim 15 , wherein said information associated with said fetched instruction comprises a branch tag based on a branch prediction from the BTB.
17. A non-transitory computer readable storage medium having encoded thereon computer readable program code for generating an apparatus comprising: a processor; an associative cache configured to store a plurality of instructions in a plurality of selectively powered ways; and an instruction fetch unit configured to fetch, for execution by said processor, a current instruction from said associative cache in accordance with an instruction pointer; wherein said processor is configured to identify a way of said associative cache in which a future instruction that is a predetermined plurality of instructions ahead of said current fetched instruction is located, using way information for the future instruction that is associated with said current fetched instruction and retrieved together with said current fetched instruction, and said identified way of said associative cache is selectively powered at a time corresponding to when that said future instruction needs to be fetched by said instruction fetch unit.