Mechanism for copying data in memory
An improved mechanism for copying data in memory is described which uses aliasing. In an embodiment, data is accessed from a first location in a memory and stored in a cache line associated with a second, different location in the memory. In response to a subsequent request for data from the second location in the memory, the cache returns the data stored in the cache line associated with the second location in the memory. The method may be implemented using additional hardware logic in the cache which is arranged to receive an aliasing request from a processor which identifies both the first and second locations in memory and triggers the accessing of data from the first location for storing in a cache line associated with the second location.
1. A method of accessing data from a first memory location to be copied to a second memory location of a memory, comprising:
accessing, by a cache, data stored at the first memory location; and
storing the data in the cache in a cache line associated with the second memory location and not associated with the first memory location, so that in response to a request for data stored at the second memory location, the cache returns the data stored in the cache line as the data stored in the second memory location when the data is stored in memory only in the first memory location, wherein the first memory location and the second memory location are different locations within the memory.
2. The method according to claim 1 , further comprising:
writing the stored data in the cache line to the second memory location.
3. The method according to claim 1 , further comprising:
receiving, at the cache, an aliasing request from a processor, the aliasing request identifying the first and second memory locations and wherein the accessing of the data stored at the first memory location is triggered by receipt of the aliasing request.
4. The method according to claim 3 , further comprising:
generating, at a processor, the aliasing request; and
transmitting the aliasing request to the cache.
5. The method according to claim 1 , wherein the cache is an L1 cache.
6. The method according to claim 1 , wherein the first memory location is free from any memory alignment constraint.
7. The method according to claim 1 , wherein the first memory location and the second memory location are the same size.
8. The method according to claim 1 , wherein the first memory location comprises a first memory range and the second memory location comprises a second memory range.
9. The method according to claim 1 , wherein the first memory location and the second memory location are different locations within a main memory.
10. A system comprising:
a processor; and
a cache, wherein the cache comprises a plurality of cache lines arranged to store data copied from a memory and hardware logic arranged to access data stored at a first memory location and store the data in a cache line associated with a second memory location and not associated with the first memory location, wherein the cache is configured, in response to a request for data stored at the second memory location, to return the data stored in the cache line as the data stored in the second memory location when the data is stored in the memory only in the first memory location, wherein the first memory location and the second memory location are different locations within the memory.
11. The system according to claim 10 , wherein the cache is arranged to provide the data stored in the cache line in response to a request for data stored in the second memory location.
12. The system according to claim 10 , wherein the cache is arranged to write the stored data in the cache line associated with the second memory location to the second memory location.
13. The system according to claim 10 , wherein the processor is arranged to generate an aliasing request and transmit the aliasing request to the cache, wherein the aliasing request identifies the first and second memory locations and wherein the hardware logic is further arranged to trigger the accessing of the data stored at the first memory location on receipt of the aliasing request from the processor.
14. The system according to claim 10 , wherein the cache is an L1 cache.
15. The system according to claim 10 , further comprising the memory containing the first and second memory locations.
16. The system according to claim 10 , wherein the first memory location comprises a first memory range and the second memory location comprises a second memory range.
17. A non-transitory computer readable storage medium having encoded thereon computer readable program code for generating a cache comprising a plurality of cache lines arranged to store data copied from a memory and hardware logic arranged to access data stored at a first memory location and store the data in a cache line associated with a second memory location and not associated with the first memory location, wherein the cache is configured, in response to a request for data stored at the second memory location, to return the data stored in the cache line as the data stored in the second memory location when the data is stored in memory only in the first memory location, wherein the first memory location and the second memory location are different locations within the memory.
18. A non-transitory computer readable storage medium having encoded thereon computer readable program code for generating a cache configured to perform the method of claim 1 .
19. The method according to claim 1 , wherein said storing the data in the cache comprises storing the data in the cache in a cache line associated with the second memory location and not associated with the first memory location, so that in response to a request for data stored at the second memory location, the cache line returns the data stored in the cache line as the data stored in the second memory location when the data is stored in the memory only in the first memory location and before the data is stored in the second memory location.