Horizontally-shared cache victims in multiple core processors
View Patent ↗A processor includes multiple processor core units, each including a processor core and a cache memory. Victim lines evicted from a first processor core unit's cache may be stored in another processor core unit's cache, rather than written back to system memory. If the victim line is later requested by the first processor core unit, the victim line is retrieved from the other processor core unit's cache. The processor has low latency data transfers between processor core units. The processor transfers victim lines directly between processor core units' caches or utilizes a victim cache to temporarily store victim lines while searching for their destinations. The processor evaluates cache priority rules to determine whether victim lines are discarded, written back to system memory, or stored in other processor core units' caches. Cache priority rules can be based on cache coherency data, load balancing schemes, and architectural characteristics of the processor.
1. A processor comprising:
a first processor core unit including a first processor core adapted to process first data, and a first cache memory adapted to store the first data; and
a second processor core unit including a second processor core adapted to process second data, and a second cache memory adapted to store the second data;
wherein the processor includes logic adapted to:
(i) receive a selection of a first victim line from the first cache memory;
(ii) identify a candidate line in the second cache memory by:
(a) identifying a set of potential candidate lines for the first victim line,
(b) evaluating a cache priority rule, in response to the receiving a selection of the first victim line, to prioritize the potential candidate lines for the first victim line, and
(c) selecting the candidate line from the set of potential candidate lines based on the prioritization of the potential candidate lines; and
(iii) store the first victim line in the candidate line in the second cache memory.
2. The processor of claim 1 further comprising:
logic adapted to receive a request for the first victim line from the first processor core;
logic adapted to locate the first victim line in the second cache memory; and
logic adapted to transfer the first victim line from the second cache memory to the first processor core.
3. The processor of claim 1 further comprising:
a third cache memory adapted to receive and to store the first victim line from the first processor core unit; said third cache memory adapted to identify the candidate line in the second cache memory and to store the first victim line in the identified candidate line of the second cache memory.
4. The processor of claim 1 wherein the cache priority rule is based on at least cache coherency data associated with the first victim line.
5. The processor of claim 1 wherein the cache priority rule is based on at least cache coherency data associated with the set of potential candidate lines.
6. The processor of claim 1 wherein the cache priority rule is based on at least on a load balancing scheme between at least the first and second processor core units.
7. The processor of claim 1 wherein the cache priority rule is based on at least an architectural characteristic of the processor.
8. The processor of claim 1 wherein the cache priority rule is based on an estimated performance gain of the processor associated with storing the first victim line in the selected candidate line.
9. The processor of claim 8 wherein the logic adapted to evaluate a cache priority rule includes logic adapted to determine at least one estimated performance gain for the first processor core in response to storing the first victim line in at least one of the set of potential candidate lines.
10. The processor of claim 9 , wherein the logic adapted to determine at least one estimated performance gain for the first processor core includes a plurality of incremental gain counters, wherein each incremental gain counter is associated with a portion of the first cache memory and adapted to count cache hits in the associated portion of the first cache memory.
11. The processor of claim 10 , wherein the logic adapted to determine at least one estimated performance gain for the first processor core includes an allocation counter adapted to output an allocation value based on the size of the portion of the first cache memory storing data associated with the first processor core, wherein the logic adapted to determine at least one estimated performance gain is adapted to use the allocation value to select one of the plurality of incremental gain counters, wherein the value of the selected incremental gain counter represents the estimated performance gain of the first processor core.
12. The processor of claim 8 wherein the logic adapted to evaluate a cache priority rule includes logic adapted to determine at least one estimated performance loss for the second processor core in response to storing the first victim line in at least one of the set of potential candidate lines.
13. The processor of claim 1 wherein the logic is adapted to identify the set of potential candidate lines for the first victim line by issuing cache snoops.
14. A method of operating a processor, wherein the processor comprises: (i) a first processor core unit including a first processor core adapted to process first data, and a first cache memory adapted to store the first data, and (ii) a second processor core unit including a second processor core adapted to process second data, and a second cache memory adapted to store the second data, wherein the method comprises:
receiving a selection of a first victim line from the first cache memory;
identifying a candidate line in the second cache memory by:
(i) identifying a set of potential candidate lines for the first victim line;
(ii) evaluating a cache priority rule, in response to the receiving a selection of the first victim line, to prioritize the potential candidate lines for the first victim line; and
(iii) selecting the candidate line from the set of potential candidate lines based on the prioritization of the potential candidate lines; and
storing the first victim line in the candidate line in the second cache memory.
15. A processor comprising:
a first processor core unit including a first processor core adapted to process first data, and a first cache memory adapted to store the first data; and
a second processor core unit including a second processor core adapted to process second data, and a second cache memory adapted to store the second data;
wherein the processor includes logic adapted to:
(i) receive a selection of a first victim line from the first cache memory;
(ii) identify a candidate line in the second cache memory by evaluating a cache priority rule, in response to the receiving a selection of the first victim line, to select the candidate line from a set of potential candidate lines; and
(iii) store the first victim line in the candidate line in the second cache memory;
wherein the logic is adapted to evaluate the cache priority rule by:
(i) determining an estimated performance gain of the first processor core unit associated with storing the first victim line in the selected candidate line;
(ii) determining an estimated performance loss for the second processor core unit associated with storing the first victim line in the selected candidate line, and
(iii) determining if the estimated performance gain outweighs the estimated performance loss.