Reconfigurable fabric direct memory access with multiple read or write elements
Techniques are disclosed for data manipulation. Data is obtained from a first switching element where the first switching element is controlled by a first circular buffer. Data is sent to a second switching element where the second switching element is controlled by a second circular buffer. Data is controlled by a third switching element that is controlled by a third circular buffer. The third switching element hierarchically controls the first switching element and the second switching element. Data is routed through a fourth switching element that is controlled by a fourth circular buffer. The circular buffers are statically scheduled. The obtaining data from a first switching element and the sending the data to a second switching element includes a direct memory access (DMA). The switching elements can operate as a master controller or as a slave device. The switching elements can comprise clusters within an asynchronous reconfigurable fabric.
1. A processor-implemented method for data manipulation comprising:
obtaining data from a first switching element within a plurality of switching elements wherein the first switching element is controlled by a first circular buffer; and
sending the data to a second switching element within the plurality of switching elements wherein the second switching element is controlled by a second circular buffer,
wherein a third switching element within the plurality of switching elements hierarchically controls the first switching element and the second switching element to perform a direct memory access (DMA) transfer.
2. The method of claim 1 wherein the plurality of switching elements comprises an asynchronous reconfigurable fabric.
3. The method of claim 2 wherein the asynchronous reconfigurable fabric is asynchronous with respect to system memory.
4. The method of claim 1 wherein the plurality of switching elements forms two or more clusters within a reconfigurable fabric.
5. The method of claim 4 wherein a cluster within two or more clusters is synchronized to a tic cycle boundary.
6. The method of claim 5 wherein the cluster within the two or more clusters and a second cluster within the two or more clusters operate on different tic cycles.
7. The method of claim 5 wherein the cluster within the two or more clusters and a second cluster within the two or more clusters operate on different tic clocks.
8. The method of claim 4 wherein the two or more clusters comprise a dataflow processor.
9. The method of claim 4 wherein the two or more clusters are initialized to perform an operation based on one or more agents defined in a software development kit (SDK).
10. The method of claim 1 further comprising a fourth switching element within the plurality of switching elements, wherein the fourth switching element is controlled by a fourth circular buffer.
11. The method of claim 10 wherein the first switching element reads a first data and writes the first data into the second switching element and the second switching element writes the first data into the fourth switching element.
12. The method of claim 11 wherein the fourth switching element sends acknowledgement to the third switching element after the first data is written to the fourth switching element.
13. The method of claim 10 wherein the third switching element further hierarchically controls the fourth switching element.
14. The method of claim 10 wherein the second switching element and the fourth switching element are connected in parallel with the first switching element.
15. The method of claim 1 wherein the obtaining data from a first switching element and the sending the data to a second switching element is autonomous of a third switching element within the plurality of switching elements.
16. The method of claim 1 wherein the data comprises a block of memory obtained from storage in the first switching element.
17. The method of claim 16 wherein the block of memory comprises a beginning address in the storage.
18. The method of claim 17 wherein the block of memory comprises an ending address in the storage.
19. The method of claim 18 wherein the obtaining is triggered by a start instruction stored in the first circular buffer.
20. The method of claim 1 further comprising routing the data through a fifth switching element within the plurality of switching elements wherein the fifth switching element is controlled by a fifth circular buffer.
21. The method of claim 20 wherein the fifth switching element is interposed between the first switching element and the second switching element.
22. The method of claim 1 wherein the first switching element and the second switching element comprise a return communication path to the third switching element.
23. The method of claim 22 wherein the first switching element transfers information from the second switching element to the third switching element on the return communication path.
24. A computer program product embodied in a non-transitory computer readable medium for data manipulation comprising code which causes one or more processors to perform operations of:
obtaining data from a first switching element within a plurality of switching elements wherein the first switching element is controlled by a first circular buffer; and
sending the data to a second switching element within the plurality of switching elements wherein the second switching element is controlled by a second circular buffer,
wherein a third switching element within the plurality of switching elements hierarchically controls the first switching element and the second switching element to perform a direct memory access (DMA) transfer.
25. A computer system for data manipulation comprising:
a memory which stores instructions;
one or more processors attached to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
obtain data from a first switching element within a plurality of switching elements wherein the first switching element is controlled by a first circular buffer; and
send the data to a second switching element within the plurality of switching elements wherein the second switching element is controlled by a second circular buffer,
wherein a third switching element within the plurality of switching elements hierarchically controls the first switching element and the second switching element to perform a direct memory access (DMA) transfer.