Horizontally-shared cache victims in multiple core processors
View Patent ↗A processor includes multiple processor core units, each including a processor core and a cache memory. Victim lines evicted from a first processor core unit's cache may be stored in another processor core unit's cache, rather than written back to system memory. If the victim line is later requested by the first processor core unit, the victim line is retrieved from the other processor core unit's cache. The processor has low latency data transfers between processor core units. The processor transfers victim lines directly between processor core units' caches or utilizes a victim cache to temporarily store victim lines while searching for their destinations. The processor evaluates cache priority rules to determine whether victim lines are discarded, written back to system memory, or stored in other processor core units' caches. Cache priority rules can be based on cache coherency data, load balancing schemes, and architectural characteristics of the processor.
1. A processor comprising:
a first processor core unit including a first processor core capable of processing first data and a first cache memory adapted to store first data;
and a second processor core unit including a second processor core capable of processing second data and a second cache memory adapted to store at least second data;
wherein the processor includes logic adapted to receive a selection of a first victim line from the first cache memory, to identify a candidate line in the second cache memory, and to store the first victim line in the candidate line in the second cache memory, wherein the logic adapted to identify the candidate line in the second cache memory includes logic adapted to evaluate a cache priority rule to select the candidate line from a set of potential candidate lines, wherein the cache priority rule is based on an estimated performance gain of the processor associated with storing the first victim line in the selected candidate line, wherein the logic adapted to evaluate a cache priority rule includes logic adapted to determine at least one estimated performance gain for the first processor core in response to storing the first victim line in at least one of the set of potential candidate lines, wherein the logic adapted to determine at least one estimated performance gain for the first processor core includes a plurality of incremental gain counters, wherein each incremental gain counter is associated with a portion of the first cache memory and adapted to count cache hits in the associated portion of the first cache memory, wherein the logic adapted to determine at least one estimated performance gain for the first processor core includes an allocation counter adapted to output an allocation value based on the size of the portion of the first cache memory storing data associated with the first processor core, wherein the logic adapted to determine at least one estimated performance gain is adapted to use the allocation value to select one of the plurality of incremental gain counters, wherein the value of the selected incremental gain counter represents the estimated performance gain of the first processor core.
2. The processor of claim 1 , further comprising:
logic adapted to receive a request for the first victim line from the first processor core;
logic adapted to locate the first victim line in the second cache memory; and
logic adapted to transfer the first victim line from the second cache memory to the first processor core.
3. The processor of claim 1 , further comprising:
a victim cache adapted to receive and to store the first victim line from the first processor core unit and including at least a portion of the logic adapted to identify the candidate line and to store the first victim line in the candidate line.
4. The processor of claim 1 , wherein at least a portion of the logic adapted to receive the selection of the first victim line, to identify the candidate line, and to store the first victim line in the candidate line is included in the first processor core unit.
5. The processor of claim 1 , wherein the cache priority rule is based on at least cache coherency data associated with the first victim line.
6. The processor of claim 1 , wherein the cache priority rule is based on at least cache coherency data associated with the set of potential candidate lines.
7. The processor of claim 1 , wherein the cache priority rule is based on at least on a load balancing scheme between at least the first and second processor core units.
8. The processor of claim 1 , wherein the cache priority rule is based on at least an architectural characteristic of the processor.
9. The processor of claim 1 , wherein the logic adapted to evaluate a cache priority rule includes logic adapted to determine at least one estimated performance loss for the second processor core in response to storing the first victim line in at least one of the set of potential candidate lines.
10. A computer system comprising:
a memory device adapted to store data;
an input device adapted to receive input data to the computer system; and
a processor adapted to process the input data and generate output data in response;
wherein the processor comprises:
a first processor core unit including a first processor core capable of processing first data and a first cache memory adapted to store first data; and
a second processor core unit including a second processor core capable of processing second data and a second cache memory adapted to store at least second data;
wherein the processor includes logic adapted to receive a selection of a first victim line from the first cache memory, to identify a candidate line in the second cache memory, and to store the first victim line in the candidate line in the second cache memory, wherein the logic adapted to identify the candidate line in the second cache memory comprises logic adapted to determine at least one estimated performance gain for the first processor core unit in response to storing the first victim line in at least one of the set of potential candidate lines, wherein the logic adapted to determine at least one estimated performance gain for the first processor core unit includes a plurality of incremental gain counters, wherein each incremental gain counter is associated with a portion of the first cache memory and adapted to count cache hits in the associated portion of the first cache memory, wherein the logic adapted to determine at least one estimated performance gain for the first processor core unit includes an allocation counter adapted to output an allocation value based on the size of the portion of the first cache memory storing data associated with the first processor core, wherein the logic adapted to determine at least one estimated performance gain is adapted to use the allocation value to select one of the plurality of incremental gain counters, wherein the value of the selected incremental gain counter represents the estimated performance gain of the first processor core unit.
11. A method of operating a processor in a multi-processor system, the method comprising:
receiving a selection of a first victim line from a first processor core unit, wherein the first victim line is selected for eviction from a first cache memory of the first processor core unit;
determining at least one estimated performance gain from at least one candidate line in at least one cache memory of a second processor core unit;
discarding the first victim line in response to the determination that the estimated performance gain is negative; and
storing the first victim line in the candidate line in response to the determination that the estimated performance gain is positive, wherein determining an estimated performance gain comprises:
determining an estimated performance gain for the first processor core unit from the use of the candidate line in the cache memory of the second processor core unit;
determining an estimated performance loss for the second processor core unit from the use of the candidate line in the cache memory of the second processor core unit by the first processor core unit; and
comparing the estimated performance gain for the first processor core unit with the estimated performance loss for the second processor core unit, wherein determining an estimated performance gain for the first processor core unit comprises selecting a value from one of a plurality of incremental gain counters, wherein the value of the selected incremental gain counter represents the estimated performance gain of the first processor core, wherein the incremental gain counter is selected using at least a portion of a value of an allocation counter specifying the number of cache lines of the first cache memory used by the first processor core unit.