Apparatus and method for operating a processor with an operation cache
View Patent ↗A processor includes a computation engine to produce a computed value for a set of operands. A cache stores the set of operands and the computed value. The cache is configured to selectively identify a match and a miss for a new set of operands. In the event of a match the computed value is supplied by the cache and a computation engine operation is aborted. In the event of a miss a new computed value for the new set of operands is computed by the computation engine and is stored in the cache.
1. A method, comprising:
simultaneously applying operands and a received operation code to a computation engine circuit component and a cache; using the operands at the computation engine circuit component to speculatively compute a related value based upon a speculative operation code; loading the speculative operation code and the related value into the cache; comparing the operands to stored operands in the cache to selectively identify a match and a miss; outputting from the cache a stored value in the event of a match; outputting from the computation engine circuit component a computed value in the event of a miss; and storing the received operation code, the speculative operation code, the operands, the related value and the computed value in the same cache line.
2. A processor, comprising: a computation engine circuit component to produce a computed value for a set of operands and a received operation code, wherein the computation engine circuit component uses the operands to speculatively compute a related value based upon a speculative operation code and loads the speculative operation code and the related value into the cache; and a cache to store the set of operands, the computed value, the received operation code, the speculative operation code and the related value; wherein the cache is configured to selectively identify a match and a miss for a new set of operands, wherein in the event of a match the computed value is supplied by the cache and a computation engine circuit component operation is aborted, and in the event of a miss a new computed value for the new set of operands is computed by the computation engine circuit component and is stored in the cache; and wherein the received operation code, the speculative operation code, the set of operands, the related value and the computed value are stored in the same cache line.
3. The processor of claim 2 wherein the cache has four rows or less.
4. A non-transitory computer readable storage medium comprising executable instructions to define a processor with: a computation engine circuit component to produce a computed value for a set of operands and a received operation code, wherein the computation engine circuit component uses the operands to speculatively compute a related value based upon a speculative operation code and loads the speculative operation code and the related value into the cache; and a cache to store the set of operands, the computed value, the received operation code, the speculative operation code and the related value; wherein the cache is configured to selectively identify a match and a miss for a new set of operands, wherein in the event of a match the computed value is supplied by the cache and a computation engine circuit component operation is aborted, and in the event of a miss a new computed value for the new set of operands is computed by the computation engine circuit component and is stored in the cache; and wherein the executable instructions define a cache wherein an original operation code, the speculative operation code, the set of operands, the related value and the computed value are stored in the same cache line.
5. The non-transitory computer readable storage medium of claim 4 wherein the executable instructions define a computation engine circuit component that is a divide engine to produce computed values including a quotient and a remainder.