IP Library Patent Application 16286891
Patent Application
App. No. 16/286,891

MATRIX COMPUTATION WITHIN A RECONFIGURABLE PROCESSOR FABRIC

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
16/286,891
Abstract

Techniques are disclosed for matrix computation within a reconfigurable fabric. A first matrix comprising a multiplier matrix and a second matrix comprising a multiplicand matrix are obtained for processing on a reconfigurable fabric. The first matrix and the second matrix are partitioned into submatrices. The first subset and the second subset are distributed to the plurality of processing elements. The processing elements for the first subset comprise a sequential path of adjacent processing elements within the reconfigurable fabric, where the sequential path forms a closed loop of processing elements starting and ending with a same first processing element. A partial matrix multiplication is performed at each of the subset of the plurality of processing elements. A result is output by recomposing results of the partial matrix multiplication at the subset of the plurality of processing elements that comprise the sequential path into a product matrix.

Claims (52)

1 . A processor-implemented method for matrix manipulation comprising:

obtaining, for processing on a reconfigurable fabric comprised of a plurality of processing elements, a first matrix, wherein the first matrix comprises a multiplier matrix;

obtaining, for processing on the reconfigurable fabric, a second matrix, wherein the second matrix comprises a multiplicand matrix;

partitioning the first matrix and the second matrix, respectively, into a first set of submatrices and a second set of submatrices;

distributing the first set of submatrices around a subset of the plurality of processing elements, wherein the subset of the plurality of processing elements comprises a sequential path of adjacent processing elements within the reconfigurable fabric, wherein the sequential path forms a closed loop of processing elements starting and ending with a same first processing element;

distributing the second set of submatrices around the subset of the plurality of processing elements;

performing a partial matrix multiplication at each of the subset of the plurality of processing elements that comprise a sequential path, wherein a portion of the second set of submatrices is sequentially rotated through the subset of the plurality of processing elements; and

outputting a result by recomposing results of the partial matrix multiplication at the subset of the plurality of processing elements that comprises the sequential path into a product matrix.

2 . The method of claim 1 wherein the performing the partial matrix multiplication is accomplished using the first set of submatrices and the portion of the second set of submatrices.

3 . The method of claim 2 further comprising performing a second partial matrix multiplication at each of the subset of the plurality of processing elements.

4 . The method of claim 3 wherein the second partial matrix multiplication is accomplished using the first set of submatrices and a second portion of the second set of submatrices.

5 . The method of claim 4 wherein the second portion of the second set of submatrices is sequentially rotated through the subset of the plurality of processing elements.

6 . The method of claim 3 wherein the recomposing is performed after the partial matrix multiplication and the second partial matrix multiplication.

7 . (canceled)

8 . The method of claim 1 wherein the distributing of the first set of submatrices and the distributing of the second set of submatrices is accomplished using direct memory access (DMA) operations from another memory into the subset of the plurality of processing elements.

9 . The method of claim 1 wherein the partitioning the first matrix separates the first matrix into pairs of columns.

10 . The method of claim 1 wherein the partitioning the first matrix separates the first matrix into pairs of rows.

11 . The method of claim 1 wherein the partitioning the second matrix separates the second matrix into pairs of columns.

12 . The method of claim 1 wherein the partitioning the second matrix separates the second matrix into pairs of rows.

13 . The method of claim 1 wherein each submatrix of the first set of submatrices is a square matrix with smaller dimensions than the first matrix.

14 . The method of claim 13 wherein the square matrix dimension of the first set of submatrices is a power of 2.

15 . (canceled)

16 . The method of claim 1 wherein each submatrix of the second set of submatrices is a square matrix with smaller dimensions than the second matrix.

17 . The method of claim 16 wherein the square matrix dimension of the second set of submatrices is a power of 2.

18 . (canceled)

19 . The method of claim 1 wherein the partitioning is done on a row basis.

20 . The method of claim 1 wherein the partial matrix multiplication comprises a multiply-accumulate function.

21 . The method of claim 1 further comprising padding one or more of the first set of submatrices with zeros when the first matrix partitions unevenly into submatrices around a ring defined by the distributing.

22 . The method of claim 1 further comprising adding one or more dummy submatrices to the second set of submatrices when the number of second-set submatrices is less than the number of first-set submatrices.

23 - 25 . (canceled)

26 . The method of claim 1 wherein the processing elements are controlled by a rotating circular buffer.

27 . (canceled)

28 . The method of claim 26 wherein the processing elements each complete their multiply operation in one tick cycle.

29 - 35 . (canceled)

36 . A computer program product embodied in a non-transitory computer readable medium for matrix manipulation, the computer program product comprising code which causes one or more processors to perform operations of:

obtaining, for processing on a reconfigurable fabric comprised of a plurality of processing elements, a first matrix, wherein the first matrix comprises a multiplier matrix;

obtaining, for processing on the reconfigurable fabric, a second matrix, wherein the second matrix comprises a multiplicand matrix;

partitioning the first matrix and the second matrix, respectively, into a first set of submatrices and a second set of submatrices;

distributing the first set of submatrices around a subset of the plurality of processing elements, wherein the subset of the plurality of processing elements comprises a sequential path of adjacent processing elements within the reconfigurable fabric, wherein the sequential path forms a closed loop of processing elements starting and ending with a same first processing element;

distributing the second set of submatrices around the subset of the plurality of processing elements;

performing a partial matrix multiplication at each of the subset of the plurality of processing elements that comprise a sequential path, wherein a portion of the second set of submatrices is sequentially rotated through the subset of the plurality of processing elements; and

outputting a result by recomposing results of the partial matrix multiplication at the subset of the plurality of processing elements that comprise the sequential path into a product matrix.

37 . A computer system for matrix manipulation comprising:

a memory which stores instructions;

one or more processors attached to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:

obtain, for processing on a reconfigurable fabric comprised of a plurality of processing elements, a first matrix, wherein the first matrix comprises a multiplier matrix;

obtain, for processing on the reconfigurable fabric, a second matrix, wherein the second matrix comprises a multiplicand matrix;

partition the first matrix and the second matrix, respectively, into a first set of submatrices and a second set of submatrices;

distribute the first set of submatrices around a subset of the plurality of processing elements, wherein the subset of the plurality of processing elements comprises a sequential path of adjacent processing elements within the reconfigurable fabric, wherein the sequential path forms a closed loop of processing elements starting and ending with a same first processing element;

distribute the second set of submatrices around the subset of the plurality of processing elements;

perform a partial matrix multiplication at each of the subset of the plurality of processing elements that comprise a sequential path, wherein a portion of the second set of submatrices is sequentially rotated through the subset of the plurality of processing elements; and

output a result by recomposing results of the partial matrix multiplication at the subset of the plurality of processing elements that comprise the sequential path into a product matrix.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Dec 29, 2022
From: CAPITAL FINANCE ADMINISTRATION, LLC, AS ADMINISTRATIVE AGENT
To: MIPS TECH, LLC; WAVE COMPUTING INC.
Reel/Frame 062251/0251 →
SECURITY INTEREST Recorded Jun 14, 2021
From: MIPS TECH, LLC; WAVE COMPUTING, INC.
To: CAPITAL FINANCE ADMINISTRATION, LLC
Reel/Frame 056558/0903 →
RELEASE OF SECURITY INTEREST Recorded Jun 14, 2021
From: WAVE COMPUTING LIQUIDATING TRUST
To: MIPS TECH, INC.; HELLOSOFT, INC.; WAVE COMPUTING (UK) LIMITED; IMAGINATION TECHNOLOGIES, INC.; CAUSTIC GRAPHICS, INC.; MIPS TECH, LLC; WAVE COMPUTING, INC.
Reel/Frame 056589/0606 →
SECURITY INTEREST Recorded Feb 26, 2021
From: WAVE COMPUTING, INC.; MIPS TECH, LLC; MIPS TECH, INC.; HELLOSOFT, INC.; WAVE COMPUTING (UK) LIMITED; IMAGINATION TECHNOLOGIES, INC.; CAUSTIC GRAPHICS, INC.
To: WAVE COMPUTING LIQUIDATING TRUST
Reel/Frame 055429/0532 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2019
From: SCOTT, DAVID ST CLAIR; ST. JOHN, THOMAS WILLIAM
To: WAVE COMPUTING, INC.
Reel/Frame 048481/0332 →