Alignment and ordering of vector elements for single instruction multiple data processing
The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.
1. A microcomputer system, comprising:
a register file comprising a plurality of registers;
a load/store unit coupled to the register file and configured to use a first part of a memory address to load a double-word into a first register and a second register of the register file; and
a control unit configured to select either an alignment unit or a shuffle unit,
wherein the alignment unit is configured to perform an alignment operation by determining a starting data byte of a vector based one of a value stored in a register and an immediate value of an instruction, such vector being stored partially in a first register and partially in a second register of the register file, and extracting the vector from the first register and the second register beginning from a first bit in a starting data byte in the first register continuing through bits in the second register and replicating the vector into a third register such that the third register contains a plurality of aligned data elements, and
wherein the shuffle unit, coupled to the register file, selects one or more data elements from at least two registers of the register file, shuffles the order of the selected data elements and writes the reordered data elements into either a selected memory location or an additional register.
2. The microcomputer system of claim 1 , wherein the shuffle unit is configured to select the first and second plurality of data elements and is configured to write the first and second plurality of data elements into the third register in an order specified by control signals.
3. The microcomputer system of claim 1 , wherein the shuffle unit is configured to select the first and second plurality of data elements and is configured to write the first and second plurality of data elements into the third register in an order specified by a shuffle instruction.
4. The microcomputer system of claim 1 , wherein the shuffle unit is configured to select one or more of odd elements, even elements, lower elements or upper elements from the first register and the second register to form the first plurality of data elements and second plurality of data elements thereby interleaving or de-interleaving data in the first and second registers.
5. The microcomputer system of claim 1 , wherein the shuffle unit is configured to convert data stored in a first size format in the first and second registers into a second size format in the third register by reading one or more of odd elements, even elements, lower elements or upper elements from the first and second registers to form the respective first and second plurality of data elements.
6. The microcomputer system of claim 1 , wherein data elements stored in the first and second registers are part of data elements in a matrix and the shuffle unit is configured to transpose a portion of the matrix by reading one or more of odd elements, even elements, lower elements or upper elements from the first and second registers to form the respective first and second plurality of data elements.
7. The microprocessor of claim 1 , wherein aligned data elements in the first and second registers are part of data elements in an array and the shuffle unit is configured to invert data elements of the array by reading one or more of odd elements, even elements, lower elements or upper elements from the first and second registers to form the respective first and second plurality of data elements.
8. The microcomputer system of claim 1 , further comprising:
a single instruction multiple data (SIMD) processing unit coupled to the register file and configured to operate on the aligned data elements in the third register.
9. A microcomputer system, comprising:
a register file comprising a plurality of registers;
an alignment unit coupled to the register file
wherein the alignment unit is configured to perform an alignment operation by determining a starting data byte of a vector based one of a value stored in a register and an immediate value of an instruction, such vector being stored partially in a first register and partially in a second register of the register file, extracting the vector from the first register and the second register beginning from a first bit in the starting data byte in the first register continuing through bits in the second register and replicating the vector into a third register such that the third register contains a plurality of aligned data elements.
10. The microcomputer system of claim 9 , wherein the alignment unit is configured to perform the alignment operation in response to control signals.
11. The microcomputer system of claim 9 , wherein the control signals specify a location of the starting byte in the first register.
12. The microcomputer system of claim 9 , wherein the alignment unit is configured to perform the alignment operation in response to an alignment instruction.
13. The microcomputer system of claim 9 , further comprising:
a single instruction multiple data (SIMD) processing unit coupled to the register file and configured to operate on the aligned data elements in the third register.
14. The microcomputer system of claim 9 , wherein the determining a starting data byte of a vector is further based on a masked data word.