Full scan solution for latched-based design
View Patent ↗A full-scan latch is provided that may be used to incorporate design for test functionality in an integrated circuit. The full-scan latch includes a shadow latch, a multiplexer, and a slave latch. The full-scan latch has a test mode and a normal mode. When in the normal mode, the device operates as a transparent latch, passing a data input to its output. When in test mode, the device is operable to pass scan data down a scan chain and to inject scan data into the data path.
1. A method, comprising:
inserting a master latch between a first logic block and a second logic block;
inserting a shadow latch coupled to a scan chain, the shadow latch receiving a scan chain signal from the scan chain;
inserting a multiplexer that receives a data signal from the second logic block and a scan chain signal from the shadow latch, the multiplexer operable to select the data signal or the scan chain signal and to produce a multiplexer output using the selected signal; and
inserting a slave latch coupled to the multiplexer and to the scan chain, the slave latch operable to receive the multiplexer output.
2. The method of claim 1 wherein the slave latch is operable to capture the data signal from the second logic block or the scan chain signal from the shadow latch and to pass the captured signal through the scan chain.
3. The method of claim 1 wherein the shadow latch is phi1-sensitive.
4. The method of claim 1 wherein the shadow latch is phi2-sensitive.
5. The method of claim 1 wherein the master latch and the shadow latch are each clocked using a buffered clock signal.