Microprocessor with improved data stream prefetching

1. A microprocessor coupled to a system memory, the microprocessor comprising:

a load request signal, for requesting data be loaded from the system memory into the microprocessor in response to a load instruction, said load request signal including a load virtual page address;

a prefetch request signal, for requesting a cache line be prefetched from the system memory into the microprocessor in response to a prefetch instruction, said prefetch request signal including a prefetch virtual page address; and

a memory subsystem, comprising:

a first translation look-aside buffer (TLB), coupled to said load request signal, for translating said load virtual page address into a load physical page address;

a second TLB, coupled to said prefetch request signal, for translating said prefetch virtual page address into a prefetch physical page address; and

a third TLB, coupled to said load request signal, for translating said load virtual page address into said load physical page address if said load virtual page address misses in said first TLB, and coupled to said prefetch request signal, for translating said prefetch virtual page address into said prefetch physical page address if said prefetch virtual page address misses in said second TLB.

2. The microprocessor as recited in claim 1 , wherein said prefetch instruction specifies a data stream, wherein said prefetched cache line is comprised in said data stream.

3. The microprocessor as recited in claim 2 , wherein said prefetch instruction specifies a fetch-ahead distance, wherein the microprocessor monitors said load request signal to synchronously generate said prefetch request signal such that said data stream is prefetched ahead of said load request signal by at least said fetch-ahead distance.

4. The microprocessor as recited in claim 1 , wherein said second TLB is updated in response to a miss of said prefetch virtual page address in said second TLB, wherein said first TLB is updated in response to a miss of said load virtual page address in said first TLB.

5. A computer program product for use with a computing device, the computer program product comprising:

a computer usable storage medium, having computer readable program code embodied in said medium, for causing a microprocessor coupled to a system memory, said computer readable program code comprising:

first program code for providing a load request signal, for requesting data be loaded from the system memory into the microprocessor in response to a load instruction, said load request signal including a load virtual page address;

second program code for providing a prefetch request signal, for requesting a cache line be prefetched from the system memory into the microprocessor in response to a prefetch instruction, said prefetch request signal including a prefetch virtual page address; and

third program code for providing a memory subsystem, comprising:

a first translation look-aside buffer (TLB), coupled to said load request signal, for translating said load virtual page address into a load physical page address;

a second TLB, coupled to said prefetch request signal, for translating said prefetch virtual page address into a prefetch physical page address; and

a third TLB, coupled to said load request signal, for translating said load virtual page address into said load physical page address if said load virtual page address misses in said first TLB, and coupled to said prefetch request signal, for translating said prefetch virtual page address into said prefetch physical page address if said prefetch virtual page address misses in said second TLB.

6. The computer program product as recited in claim 5 , wherein said prefetch instruction specifies a data stream, wherein said prefetched cache line is comprised in said data stream.

7. The computer program product as recited in claim 6 , wherein said prefetch instruction specifies a fetch-ahead distance, wherein the microprocessor monitors said load request signal to synchronously generate said prefetch request signal such that said data stream is prefetched ahead of said load request signal by at least said fetch-ahead distance.

8. The computer program product as recited in claim 5 , wherein said second TLB is updated in response to a miss of said prefetch virtual page address in said second TLB, wherein said first TLB is updated in response to a miss of said load virtual page address in said first TLB.

9. A microprocessor coupled to a system memory, the microprocessor comprising:

a load unit, for generating a load request to load data from the system memory into the microprocessor in response to a load instruction, said load request including a load virtual page address;

N stream prefetch engines, for generating N respective prefetch requests to prefetch a cache line into the microprocessor from N respective data streams in the system memory, said N respective data streams specified by N respective stream prefetch instructions, said N respective prefetch requests each including a prefetch virtual page address; and

a memory subsystem, comprising:

a load/store translation look-aside buffer (TLB), coupled to translate said load virtual page address into a load physical page address; and

N prefetch TLBs, coupled to translate said N respective prefetch virtual page addresses into N respective prefetch physical page addresses;

wherein said N is greater than 1.

10. The microprocessor as recited in claim 9 , wherein each of said N respective stream prefetch instructions specifies a fetch-ahead distance, wherein the microprocessor monitors said load request to synchronously generate at least one of said N respective prefetch requests such that a corresponding at least one of said N respective data streams is prefetched ahead of said load request by at least said fetch-ahead distance.

11. The microprocessor as recited in claim 9 , wherein said N prefetch TLBs are updated in response to a miss of said N respective prefetch virtual page addresses in said N prefetch TLBs, wherein said load/store TLB is updated in response to a miss of said load virtual page address in said load/store TLB.

12. A computer program product for use with a computing device, the computer program product comprising:

a computer usable storage medium, having computer readable program code embodied in said medium, for causing a microprocessor coupled to a system memory, said computer readable program code comprising:

first program code for providing a load unit, for generating a load request to load data from the system memory into the microprocessor in response to a load instruction, said load request including a load virtual page address;

second program code for providing N stream prefetch engines, for generating N respective prefetch requests to prefetch a cache line into the microprocessor from N respective data streams in the system memory, said N respective data streams specified by N respective stream prefetch instructions, said N respective prefetch requests each including a prefetch virtual page address; and

third program code for providing a memory subsystem, comprising:

a load/store translation look-aside buffer (TLB), coupled to translate said load virtual page address into a load physical page address; and

N prefetch TLBs, coupled to translate said N respective prefetch virtual page addresses into N respective prefetch physical page addresses;

wherein said N is greater than 1.

13. The computer program product as recited in claim 12 , wherein each of said N respective stream prefetch instructions specifies a fetch-ahead distance, wherein the microprocessor monitors said load request to synchronously generate at least one of said N respective prefetch requests such that a corresponding at least one of said N respective data streams is prefetched ahead of said load request by at least said fetch-ahead distance.

14. The computer program product as recited in claim 12 , wherein said N prefetch TLBs are updated in response to a miss of said N respective prefetch virtual page addresses in said N prefetch TLBs, wherein said load/store TLB is updated in response to a miss of said load virtual page address in said load/store TLB.