Prefetching hints
View Patent ↗A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for refill operations, and a second portion which identifies a destination.
1. A method comprising:
issuing an instruction, wherein the instruction includes a hint field, wherein the hint field specifies a prefetch behavior including a destination cache way, and a prefetch target field, wherein the prefetch target field specifies a composition of a prefetch target address;
forming the prefetch target address in accordance with the prefetch target field; and
performing a prefetch operation on at least one cache memory, wherein the prefetch operation prepares at least one cache memory location for use with a subsequent instruction.
2. The method of claim 1 , wherein performing the prefetch operation includes determining whether data stored at the prefetch target address is available in at least one cache memory location.
3. The method of claim 2 , further comprising:
retrieving the data from the prefetch target address and storing the data in the cache memory location in the destination cache way in response to the determination that the data stored at the prefetch target address is not available in the cache memory location.
4. The method of claim 3 , wherein retrieving the data from the prefetch target address includes a shared memory read.
5. The method of claim 3 , wherein retrieving the data from the prefetch target address includes an exclusive memory read.
6. The method of claim 1 , wherein the prefetch behavior indicates that the subsequent instruction is a load operation.
7. The method of claim 1 , wherein the prefetch behavior indicates that the subsequent instruction requires shared access to data stored at the prefetch target address.
8. The method of claim 1 , wherein the prefetch behavior indicates that the subsequent instruction is a store operation.
9. The method of claim 1 , wherein the prefetch behavior indicates that the subsequent instruction requires exclusive access to data stored at the prefetch target address.
10. The method of claim 1 , wherein the prefetch target field includes at least one reference to data outside of the instruction to be used to compose the prefetch target address.
11. The method of claim 10 , wherein the reference identifies a register storing a base memory address.
12. The method of claim 11 , wherein the prefetch target field includes an offset value to be added to the base memory address to form the prefetch target address.
13. The method of claim 11 , wherein the prefetch target field includes a second reference identifying a second register storing an offset value, wherein the offset value is to be added to the base memory address to form the prefetch target address.
14. The method of claim 3 , wherein the destination cache way corresponds with an expected use of the data to be stored in the cache memory location.
15. The method of claim 14 , wherein the hint field indicates the data is expected to be streamed and specifies a destination cache way for streamed data.
16. The method of claim 14 , wherein the hint field indicates the data is expected to be retained and specifies a destination cache way for retained data.
17. The method of claim 1 , wherein the prefetch target address is a virtual address.
18. The method of claim 1 , wherein the cache memory is a primary cache of a microprocessor.
19. The method of claim 1 , wherein the cache memory is a secondary cache of a microprocessor.