Load/store unit for a processor, and applications thereof

1. A hardware processor that executes instructions out-of-program-order while maintaining load/store order comprising:

a load/store queue that includes a plurality of entries, each entry configured to store information associated with an instruction during execution that may be executed out-of-program-order, the information including status information indicating whether the instruction is associated with a cache miss and one or more destination register values associated with the instruction;

a load/store graduation buffer that includes a plurality of entries configured to store pointers to entries corresponding to graduated instructions in the load/store queue;

a load data queue that includes a plurality of entries, each entry configured to store information associated with a graduated instruction, the information including one or more destination values or a permission value to permit the load data queue to store data in a specified register; and

control logic coupled to the load/store queue, the load/store graduation buffer, and the load data queue and configured to determine from the status information whether a first graduated instruction is associated with a data cache hit or a data cache miss and to determine whether a write-after-write hazard exists by comparing a destination register value of the first graduated instruction with a destination register value of all of the plurality of entries in the load/store queue corresponding to graduated instructions to check for a match of destination register values indicative of a write-after-write hazard,

wherein, if the first graduated instruction is associated with a data cache hit and no write after write hazard is detected, the data that is the subject of the data cache hit is stored in a destination register specified by the particular one or more destination register values associated with the first graduated instruction, and if the first graduated instruction is associated with a data cache miss, the control logic:

allocates an entry corresponding to the first graduated instruction in the load data queue;

uses the load data queue to continue the process of retrieving the data that is the subject of the data cache miss, and

stores, when the data that is the subject of the data cache miss is retrieved, the data that is the subject of the data cache miss in the destination register of the first graduated instruction if a write-after-write hazard does not exist based on whether a match was found during the comparison of the destination register values.

2. The hardware processor of claim 1 , wherein the first graduated instruction operates to do one of read data from memory and write data to memory.

3. The hardware processor of claim 1 , wherein the first instruction reads data from a register of a coprocessor.

4. The hardware processor of claim 1 , wherein each entry of the load/store queue includes a virtual address field for storing virtual address bits, a physical address field for storing physical address bits, and a data field for storing data bits.

5. The hardware processor of claim 1 , wherein each entry of the load/store queue includes a field for storing exception information.

6. The hardware processor of claim 1 , wherein the pointers stored in the load/store graduation buffer are completion buffer identification values.

7. The hardware processor of claim 1 , wherein each entry of the load/store graduation buffer includes a field for storing exception information.

8. A system, comprising:

a hardware processor that includes

a load/store queue that includes a plurality of entries, each entry configured to store information associated with an instruction during execution that may be executed out-of-program-order, the information including status information indicating whether the instruction is associated with a cache miss and one or more destination register values associated with the instruction,

a load/store graduation buffer that includes a plurality of entries configured to store pointers to entries corresponding to graduated instructions in the load/store queue,

a load data queue that includes a plurality of entries, each entry configured to store information associated with a graduated instruction, the information including one or more destination values or a permission value to permit the load data queue to store data in a specified register, and

control logic coupled to the load/store queue, the load/store graduation buffer, and the load data queue and configured to determine from the status information whether a first graduated instruction is associated with a data cache hit or a data cache miss and to determine whether a write-after-write hazard exists by comparing a destination register value of the first graduated instruction with a destination register value of all of the plurality of entries in the load/store queue corresponding to graduated instructions to check for a match of destination register values indicative of a write-after-write hazard, and if the first graduated instruction is associated with a data cache hit and no write after write hazard is detected, the data that is the subject of the data cache hit is stored in a destination register specified by the particular one or more destination register values associated with the first graduated instruction, and if the first graduated instruction is associated with a data cache miss, the control logic:

allocates an entry corresponding to the first graduated instruction in the load data queue;

uses the load data queue to continue the process of retrieving the data that is the subject of the data cache miss, and

stores, when the data that is the subject of the data cache miss is retrieved, the data that is the subject of the data cache miss in the destination register of the first graduated instruction if a write-after-write hazard does not exist based on whether a match was found during the comparison of the destination register values; and

a memory coupled to the processor.

9. The system of claim 8 , wherein the first graduated instruction operates to do one of read data from memory and that write data to memory.

10. The system of claim 8 , wherein each entry of the load/store queue includes a virtual address field for storing virtual address bits, a physical address field for storing physical address bits, and a data field for storing data bits.

11. The system of claim 8 , wherein the pointers stored in the load/store graduation buffer are completion buffer identification values.

12. A tangible computer readable storage medium that includes computer-readable code for generating a processor, the processor comprising:

computer-readable code to generate a load/store queue that includes a plurality of entries, each entry configured to store information associated with an instruction during execution that may be executed out-of-program-order, the information including status information indicating whether the instruction is associated with a cache miss and one or more destination register values associated with the instruction;

computer-readable code to generate a load/store graduation buffer that includes a plurality of entries configured to store pointers to entries corresponding to graduated instructions in the load/store queue;

a load data queue that includes a plurality of entries, each entry configured to store information associated with a graduated instruction, the information including one or more destination values or a permission value to permit the load data queue to store data in a specified register; and

computer-readable code to generate control logic coupled to the load/store queue, the load/store graduation buffer, and the load data queue and configured to determine from the status information whether a first graduated instruction is associated with a data cache hit or a data cache miss and to determine whether a write-after-write hazard exists by comparing a destination register value of the first graduated instruction with a destination register value of all of the plurality of entries in the load/store queue corresponding to graduated instructions to check for a match of destination register values indicative of a write-after-write hazard, wherein, if the first graduated instruction is associated with a data cache hit and no write after write hazard is detected, the data that is the subject of the data cache hit is stored in a destination register specified by the particular one or more destination register values associated with the first graduated instruction, and if the first graduated instruction is associated with a data cache miss, the control logic:

allocates an entry corresponding to the first graduated instruction in the load data queue;

uses the load data queue to continue the process of retrieving the data that is the subject of the data cache miss, and

stores, when the data that is the subject of the data cache miss is retrieved, the data that is the subject of the data cache miss in the destination register of the first graduated instruction if a write-after-write hazard does not exist based on whether a match was found during the comparison of the destination register values.

13. The tangible computer readable storage medium of claim 12 , wherein the first graduated instruction operates to do one of read data from memory and that write data to memory.

14. The tangible computer readable storage medium of claim 12 , wherein each entry of the load/store queue includes a virtual address field for storing virtual address bits, a physical address field for storing physical address bits, and a data field for storing data bits.

15. The tangible computer readable storage medium of claim 12 , wherein the pointers stored in the load/store graduation buffer are completion buffer identification values.

16. The tangible computer readable storage medium of claim 12 , wherein the processor is embodied in hardware description language software.

17. The tangible computer readable storage medium of claim 12 , wherein the processor is embodied in one of Verilog hardware description language software and VHDL hardware description language software.

18. A method for maintaining uncached load/store order in a processor that executes instructions out-of-program-order, comprising:

storing information associated with memory access instructions in a load/store queue, the load/store queue having a plurality of entries, each entry configured for storing information associated with a single instruction that may be executed out-of-program-order, the information including status information indicating whether the instruction is associated with a data cache miss and one or more destination register values associated with the instruction;

storing, in a load/store graduation buffer that includes a plurality of entries, pointers to entries corresponding to graduated instructions in the load/store queue;

storing, in a load data queue that includes a plurality of entries, information associated with a graduated load/store instruction, the information including one or more destination values or a permission value to permit the load data queue to store data in a specified register;

determining from the status information whether a first graduated instruction is associated with a data cache hit or a data cache miss;

determining whether a write-after-write hazard exists by comparing a destination register value of the first graduated instruction with a destination register value of all of the plurality of entries in the load/store queue corresponding to graduated instructions to check for a match of destination register values indicative of a write-after-write hazard;

if the first graduated instruction is associated with a data cache hit and no write after write hazard is detected, the data that is the subject of the data cache hit is stored in a destination register specified by the particular one or more destination register values associated with the first graduated instruction, and if the first graduated instruction is associated with a data cache miss,

allocating an entry corresponding to the first graduated instruction in the load data queue,

using the load data queue to continue the process of retrieving the data that is the subject of the data cache miss; and

storing, when the data that is the subject of the data cache miss is retrieved, the data that is the subject of the data cache miss in the destination register of the first graduated instruction if a write-after-write hazard does not exist based on whether a match was found during the comparison of the destination register values.

19. The method of claim 18 , further comprising:

stalling processing of instructions associated with pointers stored in the load/store graduation buffer until a read request associated with a particular instruction is sent to a bus interface unit of the processor.

20. The method of claim 18 , further comprising:

stalling processing of instructions associated with pointers stored in the load/store graduation buffer until a write request associated with a particular instruction is accepted by a write-back buffer of the processor.

21. The method of claim 18 , wherein the processing step comprises:

allocating an entry for an instruction in a fill/store buffer.

22. The method of claim 18 , wherein the processing step comprises

allocating an entry for an instruction in a load data queue.