System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
View Patent ↗A processor core and a method for distributive scoreboard scheduling in an out-of-order processor pipeline are described herein. In an embodiment, control logic appends operand availability bits to each instruction. The appended operand availability bits form a distributive scoreboard for each instruction. The appended operand availability bits are propagated together with the instruction through multiple stages of the processor pipeline. An instruction dispatch buffer stores the instruction and the operand availability bits. A dispatch controller determines when an instruction is to be issued. The determination is based, at least in part, on the operand availability bits stored in the instruction dispatch buffer.
1. An hardware instruction dispatch unit for a processor that executes instructions in an instruction pipeline having a plurality of stages, the instruction dispatch unit comprising:
control logic that appends a plurality of operand availability bits to an instruction;
an instruction buffer that stores the instruction and the plurality of operand availability bits; and
an instruction dispatcher that determines when the instruction is issued to an execution unit of the processor based, at least in part, on the plurality of operand availability bits stored in the instruction buffer, wherein the plurality of operand availability bits are propagated together with the instruction through at least one stage of the instruction pipeline and wherein the plurality of operand availability bits include a value to predict availability of a source operand of the instruction in a completion buffer, and wherein the plurality of operand availability bits include a value to activate a counter.
2. The instruction dispatch unit of claim 1 , wherein the operand availability bits are propagated together with the instruction through a plurality of stages of the instruction pipeline.
3. The instruction dispatch unit of claim 1 , wherein the plurality of operand availability bits include a counter value.
4. The instruction dispatch unit of claim 1 , wherein the plurality of operand availability bits include a value to indicate availability of a source operand of the instruction in a register.
5. The instruction dispatch unit of claim 4 , wherein the register is one of a general purpose register, an accumulator register and a co-processor register.
6. The instruction dispatch unit of claim 1 , wherein the control logic includes a renaming map.
7. A hardware processor core, comprising:
an instruction dispatch unit that includes:
control logic that appends a plurality of operand availability bits to an instruction;
an instruction buffer that stores the instruction and the plurality of operand availability bits;
an instruction pipeline having a plurality of stages; and
an instruction dispatcher that determines when the instruction is issued to an execution unit of the processor based, at least in part, on the plurality of operand availability bits stored in the instruction buffer, wherein the plurality of operand availability bits are propagated together with the instruction through at least one stage of the instruction pipeline and wherein the plurality of operand availability bits include a value to predict availability of a source operand of the instruction in a completion buffer, and wherein the plurality of operand availability bits include a value to activate a counter.
8. The processor core of claim 7 , wherein the operand availability bits are propagated together with the instruction through a plurality of stages of the instruction pipeline.
9. The processor core of claim 7 , wherein the plurality of operand availability bits include a counter value.
10. The processor core of claim 7 , wherein the plurality of operand availability bits include a value to indicate availability of a source operand of the instruction in a register.
11. The processor core of claim 10 , wherein the register is one of a general purpose register, an accumulator register and a co-processor register.
12. The processor core of claim 7 , wherein the control logic includes a renaming map.
13. A computer-readable storage medium having embodied thereon computer-readable program code to generate a processor core having an out-of-order pipeline, the processor core comprising:
an instruction dispatch unit that includes:
control logic that appends a plurality of operand availability bits to an instruction;
an instruction buffer that stores the instruction and the plurality of operand availability bits; and
an instruction dispatcher that determines when the instruction is issued to an execution unit of the processor based, at least in part, on the plurality of operand availability bits stored in the instruction buffer, wherein the plurality of operand availability bits are propagated together with the instruction through at least one stage of the out-of-order pipeline and wherein the plurality of operand availability bits include a value to predict availability of a source operand of the instruction in a completion buffer, and wherein the plurality of operand availability bits include a value to activate a counter.
14. The computer readable storage medium of claim 13 , wherein the operand availability bits are propagated together with the instruction through a plurality of stages of the out-of-order pipeline.
15. The computer readable storage medium of claim 13 , wherein the plurality of operand availability bits include a counter value.
16. The computer readable storage medium of claim 13 , wherein the plurality of operand availability bits include a value to indicate availability of a source operand of the instruction in a register.
17. The computer readable storage medium of claim 16 , wherein the register is one of a general purpose register, an accumulator register and a co-processor register.
18. The computer readable storage medium of claim 13 , wherein the control logic includes a renaming map.
19. The computer readable storage medium of claim 13 , wherein the processor core is embodied in hardware description language software.
20. The computer readable storage medium of claim 13 , wherein the processor core is embodied in Verilog hardware description language software.
21. The computer readable storage medium of claim 13 , wherein the processor core is embodied in VHDL hardware description language software.
22. A hardware processor core comprising:
an instruction dispatch unit that includes:
control logic that associates a plurality of operand availability bits with an instruction;
an instruction buffer that stores the instruction and the plurality of operand availability bits;
an instruction pipeline having a plurality of stages; and
an instruction dispatcher that determines when the instruction is issued to an execution unit of the processor based, at least in part, on the plurality of operand availability bits stored in the instruction buffer, wherein the plurality of operand availability bits are propagated together with the instruction through at least one stage of the instruction pipeline and wherein the plurality of operand availability bits include a value to predict availability of a source operand of the instruction in a completion buffer, and wherein the plurality of operand availability bits include a value to activate a counter.
23. The processor core of claim 22 , wherein the operand availability bits are propagated together with the instruction through a plurality of stages of the instruction pipeline.
24. The processor core of claim 22 , wherein the plurality of operand availability bits include a counter value.
25. The processor core of claim 22 , wherein the plurality of operand availability bits include a value to indicate availability of a source operand of the instruction in a register.
26. The processor core of claim 25 , wherein the register is one of a general purpose register, an accumulator register and a co-processor register.
27. The processor core of claim 22 , wherein the control logic includes a renaming map.