System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue
View Patent ↗A processor includes a coprocessor interface unit that couples a coprocessor that executes instructions in-program order to an execution unit that executes instructions out-of-program order. The coprocessor interface unit includes a coprocessor store data queue. If data stored in a register of the coprocessor is to be stored in a register file of the execution unit, the data is transferred from the coprocessor to the coprocessor store data queue. A graduation unit coupled to the coprocessor is also provided. The graduation unit provides a signal to the coprocessor that determines whether an instruction executed by the coprocessor is permitted to alter an architectural state of the processor.
1. A processor, comprising:
a coprocessor that executes instructions in-program order;
an execution unit that executes instructions out-of-program order;
a coprocessor interface unit that couples the coprocessor to the execution unit, the coprocessor interface unit including a coprocessor store data queue that is configured to store a result of an instruction executed by the coprocessor;
a completion buffer configured to store one or more codes associated with each instruction executed by the co-processor;
a graduation unit coupled to the coprocessor and configured to synchronize the coprocessor and the execution unit by graduating instructions in-program order by providing a signal to the coprocessor, based on the one or more codes in the completion buffer, that determines whether the result in the coprocessor store data queue is permitted to alter an architectural state of the processor.
2. The processor of claim 1 , wherein the coprocessor interface unit includes a coprocessor load data queue that stores data received from the execution unit until an instruction that operates upon the data is present within the coprocessor.
3. The processor of claim 1 , wherein if data stored in a register of the coprocessor is to be stored in memory, the data is transferred from the coprocessor to a load/store unit of the execution unit.
4. The processor of claim 1 , wherein the coprocessor interface unit includes a condition code queue that stores condition codes generated by the coprocessor.
5. The processor of claim 1 , wherein the coprocessor interface unit includes an instruction queue that stores instructions to be executed by the coprocessor.
6. The processor of claim 1 , wherein the coprocessor interface unit couples a floating point coprocessor to the execution unit.
7. The processor of claim 1 , wherein the coprocessor interface unit couples a graphics coprocessor to the execution unit.
8. A system, comprising:
a processor that includes
a coprocessor that executes instructions in-program order;
an execution unit that executes instructions out-of-program order;
a coprocessor interface unit that couples the coprocessor to the execution unit, the coprocessor interface unit including a coprocessor store data queue that is configured to store a result of an instruction executed by the coprocessor;
a completion buffer configured to store one or more codes associated with each instruction executed by the co-processor;
a graduation unit coupled to the coprocessor and configured to synchronize the coprocessor and the execution unit by graduating instructions in-program order by providing a signal to the coprocessor, based on the one or more codes in the completion buffer, that determines whether the result in the coprocessor store data queue is permitted to alter an architectural state of the processor; and
a memory coupled to the processor.
9. The system of claim 8 , wherein the coprocessor interface unit includes a coprocessor load data queue that stores data received from the execution unit until an instruction that operates upon the data is present within the coprocessor.
10. The system of claim 8 , wherein if data stored in a register of the coprocessor is to be stored in the memory, the data is transferred from the coprocessor to a load/store unit of the execution unit.
11. The system of claim 8 , wherein the coprocessor interface unit includes a condition code queue that stores condition codes generated by the coprocessor.
12. The system of claim 8 , wherein the coprocessor interface unit includes an instruction queue that stores instructions to be executed by the coprocessor.
13. The system of claim 8 , wherein the coprocessor interface unit couples a floating point coprocessor to the execution unit.
14. The system of claim 8 , wherein the coprocessor interface unit couples a graphics coprocessor to the execution unit.
15. A tangible computer readable storage medium that includes a processor embodied in software, the processor comprising:
a coprocessor that executes instructions in-program order;
an execution unit that executes instructions out-of-program order;
a coprocessor interface unit that couples the coprocessor to the execution unit, the coprocessor interface unit including a coprocessor store data queue that is configured to store a result of an instruction executed by the coprocessor;
a completion buffer configured to store one or more codes associated with each instruction executed by the co-processor;
a graduation unit coupled to the coprocessor and configured to synchronize the coprocessor and the execution unit by graduating instructions in-program order by providing a signal to the coprocessor, based on the one or more codes in the completion buffer, that determines whether the result in the coprocessor store data queue is permitted to alter an architectural state of the processor.
16. The tangible computer readable storage medium of claim 15 , wherein the coprocessor interface unit includes a coprocessor load data queue that stores data received from the execution unit until an instruction that operates upon the data is present within the coprocessor.
17. The tangible computer readable storage medium of claim 15 , wherein if data stored in a register of the coprocessor is to be stored in memory, the data is transferred from the coprocessor to a load/store unit of the execution unit.
18. The tangible computer readable storage medium of claim 15 , wherein the coprocessor interface unit includes a condition code queue that stores condition codes generated by the coprocessor.
19. The tangible computer readable storage medium of claim 15 , wherein the coprocessor interface unit includes an instruction queue that stores instructions to be executed by the coprocessor.
20. The tangible computer readable storage medium of claim 15 , wherein the processor is embodied in hardware description language software.
21. The tangible computer readable storage medium of claim 20 , wherein the processor is embodied in one of Verilog hardware description language software and VHDL hardware description language software.