External trace synchronization via periodic sampling

1. A tracing system, stored in a non-transitory computer readable medium, for a multi-tasking embedded pipelined processor having a processor core for executing instructions and trace generation logic that is operative to periodically generate trace synchronization information, the tracing system comprising:

a trace tap point located at a position in the pipeline of the pipelined processor after which instructions can no longer be killed;

a compression module, located at a position in the pipeline of the pipelined processor after which instructions can no longer be killed and coupled to the trace tap point via a first lead, wherein the compression module compresses immediately available data received from the first lead; and

a load order determination module, located at a position in the pipeline of the pipelined processor after which instructions can no longer be killed and coupled to the trace tap point via a second lead, for tracing immediately available load data from cache memory received from the second lead, wherein the load order determination module includes an input node to receive deferred load data from memory and an output node connected to a load data compression module.

2. The tracing system of claim 1 wherein the immediately available data comprises program counter, load address, store address, and store data.

3. The tracing system of claim 1 wherein the deferred load data is accompanied by an out-of-order indicator.

4. The tracing system of claim 3 wherein the out-of-order indicator indicates the relative position of one deferred load from among a plurality of deferred loads.

5. The tracing system of claim 1 wherein the compression module is configured to dynamically select from the outputs of a plurality of compression options.

6. The tracing system of claim 5 wherein the compression module compresses both immediately available data and deferred load data.

7. The tracing system of claim 1 further comprising compression selection logic operative to compare a plurality of compression results for a data type and select the most efficient compression result.

8. The tracing system of claim 7 further comprising an indicator to indicate the selected compression result.

9. A tracing method, comprising:

detecting a tracing trigger associated with execution of program code in at least one pipeline of at least one microprocessor core;

providing a full program counter value in response to detecting the tracing trigger to trace regeneration software;

referencing a plurality of traced addresses to the full program counter;

providing the referenced plurality of traced addresses to the trace regeneration software;

detecting a synchronization event; and

providing trace synchronization information in response to the synchronization event to the trace regeneration software, the trace synchronization information including program counter information, instruction set architecture information and information that enables a determination of a characteristic of an operating state of a multi-tasking processor; wherein the providing trace synchronization information occurs after determining that the instruction associated with the providing of trace synchronization information is not a branch, a load nor a store instruction.

10. The tracing method of claim 9 further comprising compressing the trace synchronization information.

11. The tracing method of claim 9 further comprising providing trace synchronization information for a load instruction.

12. The tracing method of claim 9 further comprising providing compressed trace synchronization information for a load instruction.

13. The tracing method of claim 9 further comprising providing trace synchronization information for a store instruction.

14. The tracing method of claim 9 further comprising providing compressed trace synchronization information for a store instruction.