Trace control from hardware and software
View Patent ↗A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.
1. A tracing system, comprising:
an embedded processor, said embedded processor including, a processor core for executing instructions;
trace generation logic controlled by hardware input signals, by a software-settable trace control register and by a second trace control register, the second trace control register indicating to the trace generation logic a location of a trace memory and when to transmit synchronization information to the trace memory;
compression logic for compressing the synchronization information; and
trace regeneration means for reacquiring a full program counter value after loss of a portion of trace data.
2. The tracing system of claim 1 , wherein the second trace control register includes at least one bit to indicate the location of the trace memory.
3. The tracing system of claim 1 wherein the compression logic compresses the synchronization information by transmitting a difference between a present program counter value and a most recently transmitted program counter value.
4. The tracing system of claim 1 wherein the synchronization information includes one or more of the following: a delta compression of the current program counter value, one or more of the load/store addresses, ASID value, and processor mode information.
5. A tracing system, comprising:
an embedded processor, said embedded processor including, a processor core for executing instructions;
trace generation logic controlled by hardware input signals, by a software-settable trace control register and by a second trace control register, the second trace control register indicating to the trace generation logic a location of a trace memory and when to transmit synchronization information to the trace memory;
compression logic for compressing the synchronization information; and
a counter adapted to receive a value stored in the second trace control register and to initiate tracing of synchronization information at selectable periodic intervals.
6. The tracing system of claim 5 , further comprising an input for selectively configuring the trace generation logic to trace selected synchronization information.
7. The tracing system of claim 5 , wherein selected synchronization information comprises a program counter value and a processor mode.
8. The tracing system of claim 5 , wherein selected synchronization information comprises a program counter value, and an application space identity (ASID) value.
9. The tracing system of claim 5 , wherein selected synchronization information comprises a program counter value and a load/store address in response to execution of a load/store instruction by the embedded processor.
10. A tracing system, comprising:
an embedded processor, said embedded processor including, a processor core for executing instructions;
trace generation logic controlled by hardware input signals, by a software-settable trace control register and by a second trace control register, the second trace control register indicating to the trace generation logic a location of a trace memory and when to transmit synchronization information to the trace memory;
compression logic for compressing the synchronization information; and
a trace record, generated by the trace generation logic, the trace record including an indication of the embedded processor operating mode and an application space identity (ASID) value and an instruction set architecture mode (ISAM) value.
11. A tracing system, comprising:
an embedded processor, said embedded processor including, a processor core for executing instructions;
trace generation logic controlled by hardware input signals, by a software-settable trace control register and by a second trace control register, the second trace control register indicating to the trace generation logic a location of a trace memory and when to transmit synchronization information to the trace memory; and
compression logic controlled by a mode signal for selection of one of a plurality of compression engines.
12. The tracing system of claim 11 , wherein the compression logic provides a plurality of compression options that are selected in response to the type of trace data that is being traced.
13. The tracing system of claim 11 , further comprising dynamic compression logic adapted to select a compression option in response to the trace data being traced.
14. The tracing system of claim 13 , wherein the dynamic compression logic includes a plurality of compression modules and a compression selector module operative to compare the outputs of the plurality of compression modules to determine which compression option most efficiently compresses the input trace data.
15. The tracing system of claim 13 , wherein the dynamic compression logic is adapted to compress first portions of the synchronization information and to compress a second portion of the synchronization information only when the synchronization information is subsequently available.
16. The tracing system of claim 15 where the first portions of synchronization information comprise a program counter, load address, store address, and store data.
17. The tracing system of claim 16 where the second portion of synchronization information comprises load data.