Apparatus and method for controlling the exclusivity mode of a level-two cache

1. A method of controlling the exclusivity mode of a level-two cache, comprising:

invoking an exclusivity mode based on user input specifying an exclusivity mode indicator;

generating level-two cache exclusivity control information at a processor in response to the exclusivity mode indicator;

utilizing the level-two cache exclusivity control information to configure the exclusivity mode of the level-two cache;

in a first mode configured by the exclusivity mode indicator, evicting an entry in a level-one cache that is marked as clean, wherein evicting the entry includes write-allocating the entry in the level-two cache; and

in a second mode configured by the exclusivity mode indicator, invalidating the entry in the level-one cache without write-allocating the entry in the level-two cache.

2. The method of claim 1 , wherein the exclusivity mode of the level-two cache includes a first per-processor exclusivity mode that is configurable based on first level-two cache exclusivity control information generated by a first processor, and a second per-processor exclusivity mode that is configurable based on second level-two cache exclusivity control information generated by a second processor.

3. The method of claim 1 , wherein the level-two cache exclusivity control information includes at least one of a write allocation indicator associated with a write miss to the level-two cache, a line validity indicator associated with a read hit to the level-two cache, and a return data allocation indicator associated with a read miss to the level-two cache.

4. The method of claim 3 , wherein the level-two cache operates in substantially exclusive mode.

5. The method of claim 3 , wherein the level-two cache operates in substantially exclusive mode, wherein a second level-two cache is controlled by second level-two cache exclusivity control information, and wherein the second level-two cache operates in non-exclusive mode.

6. The method of claim further comprising:

in a first mode configured by the exclusivity mode indicator, operating in an exclusive caching mode for a first type of transaction and operating in anon-exclusive caching mode for a second type of transaction.

7. The method of claim 6 , wherein the level-two cache operates in a substantially exclusive caching mode for data and the non-exclusive caching mode for instructions.

8. The method of claim 1 , further comprising processing a first cache line state indicator associated with a write miss to the level-two cache.

9. The method of claim 8 , further comprising processing a second cache line state indicator from the level-two cache, wherein the second cache line state indicator is associated with a read to the level-two cache.

10. The method of claim 1 , further comprising configuring the exclusivity mode indicator in response to an exclusivity available indicator from the level-two cache.

11. The method of claim 10 , further comprising configuring the exclusivity mode indicator in response to a level-two cache present indicator from the level-two cache.

12. The method of claim 11 , further comprising an internal exclusivity control indicator at the processor in response to the exclusivity mode indicator.

13. A system, comprising:

at least one processor, each of the at least one processors with circuitry to generate level-two cache exclusivity control information in response to an exclusivity mode indicator, and with circuitry to configure the exclusivity mode indicator based on user input; and

a port to convey the level-two cache exclusivity control information;

a level-two cache, wherein an exclusivity mode of the level-two cache is configurable based on the level-two cache exclusivity control information;

an interface between each of the at least one processors and the level-two cache, and over which the level-two cache exclusivity control information generated by each of the at least one processors is conveyed; and

circuitry that:

in a first mode configured by the exclusivity mode indicator evicts an entry in a level-one cache that is marked as clean, wherein evicting the entry includes wrie-allocating the entry in the level-two cache; and

in a second mode configured by the exclusivity mode indicator, invalidates the entry in the level-one cache without write-allocating the entry in the level-two cache.

14. The system of claim 13 , wherein the exclusivity mode of the level-two cache includes a first per-processor exclusivity mode that is configurable based on first level two cache exclusivity control information generated by a first processor, and a second per-processor exclusivity mode that is configurable based on second level-two cache exclusivity control information generated by a second processor.

15. The system of claim 13 wherein the exclusivity mode indicator is configured in response to an exclusivity available indicator from the level-two cache.

16. The system of claim 13 , further comprising circuitry to generate an internal exclusivity control indicator at the at least one processor in response to the exclusivity mode indicator.

17. A processor, comprising:

circuitry to generate level-two cache exclusivity control information in response to an exclusivity mode indicator;

circuitry to configure the exclusivity mode indicator based on user input;

a port to convey the level-two cache exclusivity control information to configure an exclusivity mode of a level-two cache; and

circuitry that:

in a first mode configured by the exclusivity mode indicator, evicts an entry in a level-one cache that is marked as clean, wherein evicting the entry includes write-allocating the entry in the level-two cache; and

in a second mode configured by the exclusivity mode indicator, invalidates the entry in the level-one cache without write-allocating the entry in the level-two cache.

18. The processor of claim 17 , further comprising circuitry to disable user input associated with configuration of the exclusivity mode indicator in response to an exclusivity available indicator from the level-two cache.

19. The processor of claim 17 , further comprising circuitry to generate an internal exclusivity control indicator at the processor in response to the exclusivity mode indicator.

20. A computer readable storage medium storing executable instructions to:

configure an exclusivity mode indicator based on user input;

generate level-two cache exclusivity control information in response to an exclusivity mode indicator;

convey the level-two cache exclusivity control information to configure an exclusivity mode of a level-two cache;

in a first mode configured by the exclusivity mode indicator, evict an entry in a level-one cache that is marked as clean, wherein evicting the entry includes write-allocating the entry in the level-two cache; and

in a second mode configured by the exclusivity mode indicator, invalidate the entry in the level-one cache without write-allocating the entry in the level-two cache.

21. The method of claim 20 , wherein the exclusivity mode of the level-two cache includes a first per-processor exclusivity mode that is configurable based on first level-two cache exclusivity control information generated in response to a first exclusivity mode indicator, and a second per-processor exclusivity mode that is configurable based on second level-two cache exclusivity control information generated in response to a second exclusivity mode indicator.

22. The computer readable storage medium of claim 20 , further comprising executable instructions to disable user input associated with configuration of the exclusivity mode indicator in response to an exclusivity available indicator from the level-two cache.

23. The computer readable storage medium of claim 20 , further comprising executable instructions to generate an internal exclusivity control indicator in response to the exclusivity mode indicator.