Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof
View Patent ↗The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a digital system is provided that includes a first digital circuit that operates at a first rate determined by a first clock signal and a second digital circuit that operates at a second rate determined by a second clock signal. The first digital circuit is coupled to the second digital circuit by a bus that is used for communications between the first digital circuit and the second digital circuit. A clock ratio controller is used to adjust the frequency of the first clock signal and/or the second clock signal in response to a power management signal without causing a loss of synchronization between the first digital circuit and the second digital circuit.
1. A method for controlling power in a digital system, comprising:
(1) identifying a first clock signal that can be adjusted to reduce power consumption by a first digital circuit;
(2) generating a new clock ratio;
(3) adjusting a frequency of the first clock signal during an alignment between an edge of the first clock signal and an edge of a second clock signal, wherein the second clock signal is provided to a second digital circuit that communicates with the first digital circuit via a bus coupling the second digital circuit to the first digital circuit; and
(4) maintaining the frequency ratio of the first clock signal to the second clock signal during the adjusting.
2. The method of claim 1 , further comprising:
(5) adjusting a frequency of the second clock signal.
3. The method of claim 1 , wherein:
identifying the first clock signal that can be adjusted to reduce power consumption by the first digital circuit comprises identifying a first clock signal that can be adjusted to reduce power consumption by a first digital circuit, the first digital circuit having a transmit register,
adjusting a frequency of the first clock signal during the alignment, wherein the second digital circuit includes a receive register, and
the method further comprises (5) generating strobe signals that enable operation of the transmit register and the receive register.
4. The method of claim 3 , wherein (2) comprises adjusting the frequency of the first clock signal when a strobe signal generated in (5) enables operation of the transmit register.
5. A digital system, comprising:
a second digital circuit configured to identify a first clock signal that can be adjusted to reduce power consumption by a first digital circuit;
a third digital circuit configured to generate a new clock ratio;
a fourth digital circuit configured to adjust a frequency of the first clock signal during an alignment between an edge of the first clock signal and an edge of a second clock signal, wherein the second clock signal is provided to a fifth digital circuit that communicates with the second digital circuit using a bus coupling the fifth digital circuit to the second digital circuit; and
a sixth digital circuit configured to maintain the frequency ratio of the first clock signal to the second clock signal during the adjusting by the fourth digital circuit.
6. The digital system of claim 5 , further comprising:
a seventh digital circuit configured to adjust a frequency of the second clock signal.
7. The digital system of claim 5 , wherein:
the first digital circuit has a transmit register, and
the fifth digital circuit has a receive register, and the digital system further comprises an eighth digital circuit configured to generate strobe signals that enable operation of the transmit register and the receive register.
8. The digital system of claim 7 , wherein the fourth digital circuit is further configured to adjust a frequency of the first clock signal when a strobe signal generated by the fifth digital circuit enables operation of the transmit register.
9. A computer readable storage medium having operations for creating a digital system thereon, the digital system comprising:
a second digital circuit configured to identify a first clock signal that can be adjusted to reduce power consumption by a first digital circuit;
a third digital circuit configured to generate a new clock ratio;
a fourth digital circuit configured to adjust a frequency of the first clock signal during an alignment between an edge of the first clock signal and an edge of a second clock signal, wherein the second clock signal is provided to a fifth digital circuit that communicates with the second digital circuit using a bus coupling the fifth digital circuit to the second digital circuit; and
a sixth digital circuit configured to maintain the frequency ratio of the first clock signal to the second clock signal during the adjusting by the fourth digital circuit.
10. The computer readable storage medium of claim 9 , wherein the digital system further comprises:
a seventh digital circuit configured to adjust a frequency of the second clock signal.
11. The computer readable storage medium of claim 9 , wherein:
the first digital circuit has a transmit register, and
the fifth digital circuit has a receive register, and the digital system further comprises an eighth digital circuit configured to generate strobe signals that enable operation of the transmit register and the receive register.
12. The computer readable storage medium of claim 11 , wherein the fourth digital circuit is further configured to adjust a frequency of the first clock signal when a strobe signal generated by the fifth digital circuit enables operation of the transmit register.