Method for latest producer tracking in an out-of-order processor, and applications thereof
View Patent ↗Methods for latest producer tracking in a processor. In one embodiment, the method includes the steps of (1) writing a physical register identification value in a first register rename map location specified by a first instruction, (2) writing a first in-register status value in a second register rename map location specified by the first instruction, (3) writing a producer tracking status value at a producer tracking map location specified by the physical register identification value, and (4) modifying, upon graduation of the first instruction, the first in-register status value only if the producer tracking map location stores the producer tracking status value written in step (3). Other methods are also presented.
1. A method for tracking data in a processor comprising:
a) providing a plurality of logical registers and a plurality of physical registers;
b) decoding a first instruction that produces a first result, wherein said first instruction specifies one of the plurality of logical registers as a destination register;
c) identifying one of said plurality of physical registers that is available to store the result;
d) assigning the identified available physical register to said first instruction to store the first result until graduation of said first instruction;
e) associating a producer tracking status value in a producer tracking map location with the assigned physical register; and
f) executing a second instruction wherein said second instruction uses the logical registers or the assigned one of the plurality of physical registers as a source based on the value of the producer tracking status value.
2. The method of claim 1 , wherein the plurality of logical registers comprises architectural state registers of a register file.
3. The method of claim 1 , wherein the bits comprising the instruction are stored in a processor pipeline register.
4. The method of claim 1 , wherein a portion of the first instruction provides an index value to associate one of said plurality of logical registers to a corresponding one of said plurality of physical registers.
5. The method of claim 1 , further comprising tracking physical registers being used by producing instructions.
6. The method of claim 1 , further comprising using a single bit to indicate whether a physical register is available.
7. A method for tracking data in a processor comprising:
a) providing a plurality of logical registers and a plurality of physical registers;
b) decoding a first result producing instruction;
c) in response to the decoding, changing previously existing mappings between a logical register and a corresponding physical register used by a previous result producing instruction;
d) identifying which of said plurality of physical registers are available to store a result of the first result producing instruction;
e) assigning an available one of said plurality of physical registers to said instruction to store the result until graduation of said first result producing instruction;
f) associating a producer tracking status value in a producer tracking map location with the assigned physical register; and
g) executing a second producing instruction in a pipeline register, wherein said second producing instruction utilizes the logical registers or the assigned one of said plurality of physical registers as a source based on the value of the producer tracking status value.
8. The method of claim 7 , further comprising tracking physical registers used by said previous value producing instruction.
9. The method of claim 8 , further comprising using a single bit value to identify a physical register used by said previous value producing instruction.
10. The method of claim 7 , wherein said first instruction specifies at least one of the plurality of logical registers each of which is mapped to a physical register.
11. The method of claim 10 , wherein said second instruction uses the mapped physical registers.
12. The method of claim 10 , wherein said second instruction uses the physical register assigned to store the result.
13. The method of claim 7 , further comprising generating the second instruction in a pipeline register.
14. The method of claim 7 , wherein the assigned one of the plurality of physical registers is different from the physical register used by said previous value producing instruction.
15. The method of claim 7 , wherein said first instruction specifies at least one of the plurality of logical registers each of which is mapped to a physical register.
16. A computer program product comprising a computer readable storage medium, the computer readable storage medium having encoded thereon computer program code to generate a processor, the processor comprising:
a) generating a plurality of logical registers and a plurality of physical registers;
b) decoding a first result producing instruction;
c) changing previously existing mappings between a logical register and a corresponding physical register used by a previous result producing instruction in response to the decoding;
d) identifying which of said plurality of physical registers are available to store a result of the first result producing instruction;
e) assigning an available one of said plurality of physical registers to said instruction to store the result until graduation of said first result producing instruction;
f) associating a producer tracking status value in a producer tracking map location with the assigned physical register; and
g) executing a second producing instruction in a pipeline register, wherein said second producing instruction utilizes the logical register or the assigned one of said plurality of physical registers as a source based on the value of the producer tracking status value.
17. The computer program product of claim 16 , further comprising seventh computer code to track physical registers used by said previous value producing instruction.