Microprocessor with improved data stream prefetching
View Patent ↗A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates load/store requests to transfer data between the system memory and the microprocessor. The microprocessor also includes a stream prefetch unit that generates a plurality of prefetch requests to prefetch the data stream from the system memory into the microprocessor. The prefetch requests specify the stream prefetch priority. The microprocessor also includes a bus interface unit (BIU) that generates transaction requests on the bus to transfer data between the system memory and the microprocessor in response to the load/store requests and the prefetch requests. The BIU prioritizes the bus transaction requests for the prefetch requests relative to the bus transaction requests for the load/store requests based on the stream prefetch priority.
1. A microprocessor coupled to a system memory, the microprocessor comprising:
a memory subsystem, having a translation look-aside buffer (TLB) configured to store TLB information;
an instruction decode unit, coupled to said memory subsystem, configured to decode an instruction, said instruction specifying a data stream in the system memory and an abnormal TLB access policy;
a stream prefetch unit, coupled to said memory subsystem, configured to generate a prefetch request to said memory subsystem to prefetch a cache line of said data stream from the system memory into said memory subsystem, wherein if a virtual page address of said prefetch request causes an abnormal TLB access, said memory subsystem is configured to selectively abort said prefetch request based on said abnormal TLB access policy specified in said instruction; and
a load unit, coupled to said memory subsystem, configured to generate a load request to said memory subsystem to load data specified by an address from the system memory into said memory subsystem,
wherein said instruction specifies a fetch-ahead distance, wherein said stream prefetch unit is configured to monitor said load request to determine when said address hits in said data stream, wherein said stream prefetch unit is configured to generate one or more of said prefetch request such that said data stream is prefetched into said memory subsystem at least said fetch-ahead distance ahead of said load request address hitting in said data stream.
2. The microprocessor as recited in claim 1 , wherein said abnormal TLB access policy comprises a TLB miss policy, wherein if said virtual page address of said prefetch request causes a TLB miss of said TLB, said memory subsystem is configured to selectively abort said prefetch request based on said TLB miss policy specified in said instruction.
3. The microprocessor as recited in claim 2 , wherein said memory subsystem is configured to abort said prefetch request if said TLB miss policy specifies a first predetermined value, and fetches address translation information associated with said missing virtual page address into said TLB from the system memory in response to said miss if said TLB miss policy specifies a second predetermined value.
4. The microprocessor as recited in claim 1 , wherein said abnormal TLB access policy comprises a page fault policy, wherein if said TLB information selected by said virtual page address of said prefetch request indicates a condition in which said memory page specified by said virtual page address is not present in the system memory, said memory subsystem is configured to selectively abort said prefetch request based on said page fault policy specified in said instruction.
5. The microprocessor as recited in claim 4 , wherein said memory subsystem is configured to abort said prefetch request if said page fault policy specifies a first predetermined value, and notifies an operating system executing on the microprocessor of said condition in response to detection of said condition if said page fault policy specifies a second predetermined value.
6. The microprocessor as recited in claim 1 , wherein said abnormal TLB access policy comprises a protection fault policy, wherein if said TLB information selected by said virtual page address of said prefetch request indicates a condition in which said virtual page address accessing said TLB causes a memory protection violation, said memory subsystem is configured to selectively abort said prefetch request based on said protection fault policy specified in said instruction.
7. The microprocessor as recited in claim 6 , wherein said memory subsystem is configured to abort said prefetch request if said protection fault policy specifies a first predetermined value, and is configured to notify an operating system executing on the microprocessor of said condition in response to detection of said condition if said protection fault policy specifies a second predetermined value.
8. A method for prefetching a data stream into a microprocessor from a system memory coupled to the microprocessor, the microprocessor having a translation look-aside buffer (TLB), the method comprising:
decoding an instruction, specifying the data stream, a fetch-ahead distance, and a parameter specifying an abnormal TLB access policy;
monitoring load requests generated by the microprocessor to determine if one of said load requests hits in the data stream within said fetch-ahead distance of a last prefetch from the data stream;
generating a prefetch request to prefetch a cache line of said data stream from the system memory into the microprocessor in response to said monitoring, said new request including a virtual page address of said cache line; and
selectively aborting said prefetch request if said virtual page address causes an abnormal access of said TLB, based on said abnormal TLB access policy specified in said parameter.
9. The method as recited in claim 8 , wherein said abnormal TLB access policy comprises a TLB miss policy, wherein said selectively aborting said prefetch request comprises said memory subsystem aborting said prefetch request if said TLB miss policy specifies a first predetermined value, and fetching address translation information associated with said missing virtual page address into said TLB from the system memory in response to said miss if said TLB miss policy specifies a second predetermined value.
10. The method as recited in claim 8 , wherein said abnormal TLB access policy comprises a page fault policy, wherein said selectively aborting said prefetch request comprises said memory subsystem aborting said prefetch request if said page fault policy specifies a first predetermined value, and notifying an operating system executing on the microprocessor of said condition in response to detection of said condition if said page fault policy specifies a second predetermined value.
11. The method as recited in claim 8 , wherein said abnormal TLB access policy comprises a protection fault policy, wherein said selectively aborting said prefetch request comprises said memory subsystem aborting said prefetch request if said protection fault policy specifies a first predetermined value, and notifying an operating system executing on the microprocessor of said condition in response to detection of said condition if said protection fault policy specifies a second predetermined value.
12. A computer readable storage medium, having thereon computer readable program code to generate a processor, the computer readable program code comprising:
first program code for providing a memory subsystem, having a translation look-aside buffer (TLB) for storing TLB information;
second program code for providing an instruction decode unit, coupled to said memory subsystem, for decoding an instruction, said instruction specifying a data stream in the system memory and an abnormal TLB access policy; and
third program code for providing a stream prefetch unit, coupled to said memory subsystem, for generating a prefetch request to said memory subsystem to prefetch a cache line of said data stream from the system memory into said memory subsystem, wherein if a virtual page address of said prefetch request causes an abnormal TLB access, said memory subsystem selectively aborts said prefetch request based on said abnormal TLB access policy specified in said instruction.