Processor with improved accuracy for multiply-add operations
View Patent ↗Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.
1. A hardware processor, comprising:
a load-store unit configured to provide data to other units of the processor, and to receive data from other units of the processor;
an integer execution unit to configured to perform integer operations; and
a floating point execution unit to configured to perform floating point operations, the floating point unit, comprising:
a multiplier unit configured to accept a first operand having a mantissa and a second operand having a mantissa, wherein the multiplier unit is further configured to:
multiply the first and second operands to produce a product value having a mantissa, and
round the product value to produce a multiplier output value having an internal format that includes a mantissa, the mantissa having more than one bit to the left of the binary point, wherein at least one of the more than one bits to the left of the binary point has a value of one (1);
an adder unit configured to add the multiplier output value and a third operand to form a sum value; and
an instruction fetch unit configured to fetch instructions for processing by the integer execution unit and the floating point execution unit.
2. The processor of claim 1 , wherein the multiplier unit does not normalize or denormalize the product value.
3. The processor of claim 1 , wherein the mantissa of the first operand and the mantissa of the second operand are represented by a first number of bits, and the mantissa of the product value and the mantissa of the multiplier output value are represented by a second number of bits, wherein the second number of bits is greater than the first number of bits.
4. The processor of claim 1 , wherein the multiplier unit is configurable to operate in one of a plurality of Operating modes that include a first operating mode and a second operating mode, and wherein the multiplier output mantissa conforms to an IEEE standard in the second operating mode.
5. The processor of claim 4 , wherein the multiplier output value mantissa is normalized or denormalized, as necessary, and rounded in accordance with IEEE standard.
6. The processor of claim 4 , wherein the plurality of operating modes includes a third operating mode, wherein the multiplier output mantissa is flushed to zero or other predefined values when a denormalized multiplier output is detected.
7. A computer program product comprising a tangible computer usable medium, the tangible computer usable medium having encoded thereon computer readable program code to define a processor, the computer readable program code comprising:
first computer readable program code to provide a load-store unit to provide data to other units of the processor, and receive data from other units of the processor;
second computer readable program code to provide an integer execution unit to perform integer operations; and
third computer readable program code to provide a floating point execution unit to perform floating point operations, the floating point execution unit, comprising:
fourth computer readable program code to provide a multiplier unit to receive a first operand having a mantissa and a second operand having a mantissa, wherein the multiplier unit:
multiplies the first and second operands to produce a product value, and
rounds the product value to produce a multiplier output value having an internal format characterized in having a mantissa having more than one bit to the left of the binary point, wherein at least one of the more than one bits to the left of the binary point has a value of one (1);
fifth computer readable program code to provide an adder unit to add the product value and a third operand to form a sum value; and
sixth computer readable program code to provide an instruction fetch unit to fetch instructions for processing by the integer execution unit and the floating point execution unit.
8. The computer program product of claim 7 , wherein the fourth readable program code does not normalize or denormalize the product value.
9. The computer program product of claim 7 , wherein the fourth computer program code represents the mantissa of the first operand and the mantissa of the second operand by a first number of bits, and represents the mantissa of the product value and the mantissa of the multiplier output value by a second number of bits, wherein the second number of bit is greater than the second number of bits.
10. The computer program product of claim 7 , wherein the fourth computer readable program code provides that the multiplier unit is configurable to operate in one of a plurality of operating modes that include a first operating mode and a second operating mode wherein the multiplier output mantissa conforms to an IEEE standard.
11. The computer program product of claim 10 , wherein the fourth computer readable program code provides that the multiplier output mantissa is normalized or denormalized, as necessary, and rounded in accordance with IEEE standard.
12. The computer program product of claim 10 , wherein the plurality of operating modes provided by the fourth computer readable code includes a third operating mode wherein the multiplier output mantissa is flushed to zero or other predefined values when a denormalized multiplier output is detected.
13. The computer program product of claim 10 , wherein the computer readable code is a hardware description language.
14. The computer program product of claim 13 , wherein the hardware description language is one of VHDL and AHDL.
15. A method for performing a multiply-add operation in a processor having a floating point unit that includes a multiplier unit and an adder unit, the method comprising:
receiving a first operand having a mantissa and a second operand having a mantissa;
multiplying the first and second operands, to produce a product value;
rounding the product value to produce a multiplier output value having an internal format characterized in having a mantissa having more than one bit to the left of the binary point, wherein at least one of the more than one bits to the left of the binary point has a value of one ( 1 ); and
adding the product value and a third operand to form a sum value.
16. The method of claim 15 , wherein the multiplying step does not include normalizing or denormalizing the product value.
17. The method of claim 15 , further comprising:
representing the mantissas of the first and second operands by a first number of bits; and
representing the mantissas of the product value and multiplier output value by a second number of bits, wherein the second number of bits is greater than the first number of bits.
18. The method of claim 15 , farther comprising:
operating in a one of a plurality of operating modes that include a first operating mode and a second operating mode; and
conforming the multiplier output mantissa to an IEEE standard in the second operating mode.
19. The method of claim 18 , further comprising:
normalizing or denormalizing the product output value mantissa, as necessary; and
rounding the product value in accordance with IEEE standard.
20. The method of claim 18 , wherein the plurality of operating modes includes a third operating mode, comprising:
flushing the multiplier output mantissa to zero or other predefined values when a denormalized multiplier output is detected in the third operating mode.
21. A floating point execution unit, comprising:
a multiplier unit configured to accept a first operand having a mantissa and a second operand having a mantissa, wherein the multiplier unit is configured to:
multiply the first and second operands to produce a product value having a mantissa, and
round the product value to produce a multiplier output value having an internal format that includes a mantissa, the mantissa having more than one bit to the left of the binary point, wherein at least one of the more than one bits to the left of the binary point has a value of one (1); and
an adder unit configured to add the multiplier output value and a third operand to form a sum value.
22. The floating point execution unit of claim 21 , wherein the multiplier unit does not normalize or denormalize the product value.
23. The floating point execution unit of claim 21 , wherein the mantissa of the first operand and the mantissa of the second operand are represented by a first number of bits, and the mantissa of the product value and the mantissa of the multiplier output value are represented by a second number of bits, wherein the second number of bits is greater than the first number of bits.
24. The floating point execution unit of claim 21 , wherein the multiplier unit is configurable to operate in one of a plurality of operating modes that include a first operating mode and a second operating mode wherein the multiplier output mantissa is conformed to an IEEE standard.
25. The floating point execution unit of claim 24 , wherein the multiplier output value mantissa is normalized or denormalized, as necessary, and rounded in accordance with IEEE standard.
26. The floating point execution unit of claim 24 , wherein the plurality of operating modes includes a third operating mode wherein the multiplier output mantissa is flushed to zero or other predefined values when a denormalized multiplier output is detected.