Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline
A processor core and method for managing program counter redirection in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.
1 . A non-transitory computer-readable storage medium having stored thereon computer-readable program code to generate a processor core having an out-of-order pipeline, the processor core comprising:
an instruction identification generator that generates instruction identification tags used to identify a program order of instructions; and
a mispredict instruction identification checker that compares a first instruction identification tag associated with a first control transfer instruction to a second instruction identification tag stored in a register of the mispredict instruction identification checker, the second identification tag being associated with a second control transfer instruction,
wherein if the comparison of the first instruction identification tag and the second instruction identification tag indicates that the first control transfer instruction executed out of program order relative to the second control transfer instruction, the mispredict instruction identification checker generates a signal that enables instruction fetching to be redirected in accordance with a program counter value associated with the first control transfer instruction.
2 . The computer readable storage medium of claim 1 , wherein the register of the mispredict instruction identification checker stores a valid value.
3 . The computer readable storage medium of claim 1 , wherein the mispredict instruction identification checker includes a first register and a second register, the first register used to store instruction identification tags of instructions associated with a first program thread and the second register used to store instruction identification tags of instructions associated with a second program thread.
4 . The computer readable storage medium of claim 1 , wherein a first set of instruction identification tags are generated for instructions associated with a first program thread and a second set of instruction identification tags are generated for instructions associated with a second program thread.
5 . The computer readable storage medium of claim 1 , wherein the processor core is embodied in hardware description language software.
6 . The computer readable storage medium of claim 5 , wherein the processor core is embodied in Verilog hardware description language software.
7 . The method of claim 13 , wherein the register of the mispredict instruction identification checker stores a valid value.
8 . The computer program product of claim 13 , wherein the mispredict instruction identification checker includes a first register and a second register, the first register used to store instruction identification tags of instructions associated with a first program thread and the second register used to store instruction identification tags of instructions associated with a second program thread.
9 . The computer program product of claim 13 , wherein a first set of instruction identification tags are generated for instructions associated with a first program thread and a second set of instruction identification tags are generated for instructions associated with a second program thread.
10 . The computer program product of claim 13 , wherein the processor core is embodied in hardware description language software.
11 . The method of claim 13 , wherein the transmitting step comprises transmitting the computer-readable program code over the Internet.
12 . The computer readable storage medium of claim 5 , wherein the processor core is embodied in VHDL hardware description language software.
13 . A non-transitory computer-readable storage medium having stored thereon computer-readable program code to generate a processor core having an out-of-order pipeline, the processor core comprising:
first computer readable program code for providing an instruction identification generator that generates instruction identification tags used to identify a program order of instructions; and
second computer readable program code for providing a mispredict instruction identification checker that compares a first instruction identification tag associated with a first control transfer instruction to a second instruction identification tag stored in a register of the mispredict instruction identification checker, the second identification tag being associated with a second control transfer instruction,
wherein if the comparison of the first instruction identification tag and the second instruction identification tag indicates that the first control transfer instruction executed out of program order relative to the second control transfer instruction, the mispredict instruction identification checker generates a signal that enables instruction fetching to be redirected in accordance with a program counter value associated with the first control transfer instruction.