Programmable Memory Address
A method includes storing defined memory address segments and defined memory address segment attributes for a processor. The processor is operated in accordance with the defined memory address segments and defined memory address segment attributes.
1 . A method, comprising:
storing defined memory address segments and defined memory address segment attributes; and
operating the processor in accordance with the defined memory address segments and defined memory address segment attributes.
2 . The method of claim 1 wherein storing includes storing an access permission defined memory address segment attribute.
3 . The method of claim 2 wherein storing includes storing an access permission selected from user mode, kernel mode and supervisor mode.
4 . The method of claim 1 wherein storing includes storing a cache feature defined memory address segment attribute, wherein the cache feature defines access to addresses within a defined memory address segment.
5 . The method of claim 1 wherein storing includes storing a memory map feature defined memory address segment attribute, wherein the memory map feature specifies use of a translation look-aside buffer for an address within a defined memory address segment.
6 . A computer, comprising:
a memory; and
a processor connected to the memory, wherein the processor includes memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes.
7 . The computer of claim 6 wherein the segment configuration registers store an access permission defined memory address segment attribute.
8 . The computer of claim 7 wherein the access permission is selected from user mode, kernel mode and supervisor mode.
9 . The computer of claim 6 wherein the segment configuration registers store a cache feature defined memory address segment attribute, wherein the cache feature defines access to addresses within a defined memory address segment.
10 . The computer of claim 6 wherein the segment configuration registers store a map feature defined memory address segment attribute, wherein the map feature specifies use of a translation look-aside buffer for an address within a defined memory address segment.
11 . The computer of claim 6 wherein the segment configuration registers store a memory segment index size.
12 . A processor, comprising:
memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes.
13 . The processor of claim 12 wherein the memory segment configuration registers store an access permission defined memory address segment attribute.
14 . The processor of claim 13 wherein the access permission is selected from user mode, kernel mode and supervisor mode.
15 . The processor of claim 12 wherein the memory segment configuration registers store a cache feature defined memory address segment attribute, wherein the cache feature defines access to addresses within a defined memory address segment.
16 . The computer of claim 12 wherein the memory segment configuration registers store a map feature defined memory address segment attribute, wherein the map feature specifies use of a translation look-aside buffer for an address within a defined memory address segment.
17 . A computer readable storage medium including executable instructions to define a processor, comprising:
memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes.
18 . The computer readable storage medium of claim 17 wherein the memory segment configuration registers store an access permission defined memory address segment attribute.
19 . The computer readable storage medium of claim 17 wherein the memory segment configuration registers store a cache feature defined memory address segment attribute, wherein the cache feature defines access to addresses within a defined memory address segment.
20 . The computer readable storage medium of claim 17 wherein the memory segment configuration registers store a map feature defined memory address segment attribute, wherein the map feature specifies use of a translation look-aside buffer for an address within a defined memory address segment.
21 . The computer readable storage medium of claim 17 wherein the segment configuration registers store a memory segment index size.