Processor core and method for managing branch misprediction in an out-of-order processor pipeline

1. A processor having an out-of-order pipeline, comprising:

an instruction fetch portion of the pipeline;

an instruction execution portion of the pipeline, coupled to the instruction fetch portion of the pipeline; and

pipeline control logic, coupled to the instruction fetch portion of the pipeline and the instruction execution portion of the pipeline, wherein the pipeline control logic:

halts movement of instructions from the instruction fetch portion of the pipeline to the instruction execution portion of the pipeline in response to a detection of a control transfer instruction misprediction resulting from a control transfer instruction comprising a control transfer instruction ID checked by a misprediction instruction ID checker;

invalidates instructions residing within the instruction fetch portion of the pipeline;

continues executing instructions in the instruction execution portion of the pipeline after detection of the control transfer instruction misprediction until the control transfer instruction reaches a selected stage of the instruction execution portion of the pipeline;

invalidates instructions residing in the instruction execution portion of the pipeline once the control transfer instruction reaches the selected stage; and

restarts transfer of instructions from the instruction fetch portion of the pipeline to the instruction execution portion of the pipeline.

2. The processor of claim 1 , wherein there are a plurality of program threads, and the pipeline control logic invalidates instructions belonging to one of the plurality of program threads associated with the control transfer instruction misprediction.

3. A computer readable storage medium comprising computer-readable program code to generate a processor having an out-of-order pipeline embodied in software, the processor comprising:

an instruction fetch portion of the pipeline;

an instruction execution portion of the pipeline, coupled to the instruction fetch portion of the pipeline; and

pipeline control logic, coupled to the instruction fetch portion of the pipeline and the instruction execution portion of the pipeline, wherein the pipeline control logic:

halts movement of instructions from the instruction fetch portion of the pipeline to the instruction execution portion of the pipeline in response to a detection of a control transfer instruction misprediction resulting from a control transfer instruction comprising a control transfer instruction ID checked by a misprediction instruction ID checker;

invalidates instructions residing within the instruction fetch portion of the pipeline;

continues executing instructions in the instruction execution portion of the pipeline after detection of the control transfer instruction misprediction until the control transfer instruction reaches a selected stage in the instruction execution portion of the pipeline;

invalidates instructions residing in the instruction execution portion of the pipeline once the control transfer instruction reaches the selected stage; and

restarts transfer of instructions from the instruction fetch portion of the pipeline to the instruction execution portion of the pipeline.

4. The computer readable storage medium of claim 3 , wherein the processor comprises a plurality of program threads, and the pipeline control logic invalidates instructions belonging to one of the plurality of program threads associated with the control transfer instruction misprediction.

5. The computer readable storage medium of claim 3 , wherein the computer-readable program code is a hardware description language software.

6. The computer readable storage medium of claim 5 , wherein the computer-readable program code is a Verilog hardware description language software.

7. The computer readable storage medium of claim 5 , wherein the computer-readable program code is a VHDL hardware description language software.

8. A method for clearing an out-of-order processor pipeline after a control transfer instruction misprediction, the method comprising:

(1) detecting a conditional program counter redirect misprediction during execution of a control transfer instruction in an instruction comprising a control transfer instruction ID checked by a misprediction instruction ID checker execution portion of a processor pipeline;

(2) halting movement of instructions from an instruction fetch portion of the processor pipeline to the instruction execution portion of the processor pipeline in response to the detected misprediction;

(3) invalidating instructions residing within the instruction fetch portion of the processor pipeline;

(4) continuing to execute instructions residing within the instruction execution portion of the processor pipeline until the control transfer instruction reaches a selected stage in the instruction execution portion of the processor pipeline;

(5) invalidating instructions in the instruction execution portion of the pipeline once the control transfer instruction reaches the selected stage; and

(6) restarting transfer of instructions from the instruction fetch portion of the pipeline to the instruction execution portion of the pipeline.

9. The method of claim 8 , wherein (1) comprises detecting a conditional program counter redirect misprediction during execution of one of a branch instruction and a jump instruction.

10. The method of claim 8 , further comprising recoding at least one compressed format instruction.

11. The method of claim 8 , wherein there are a plurality of program threads, and (3) comprises invalidating instructions belonging to one of the plurality of program threads associated with the control transfer instruction.

12. The method of claim 8 , wherein there are a plurality of program threads, and (4) comprises invalidating instructions belonging to one of the plurality of program threads associated with the control transfer instruction.

13. A processor, comprising:

a pipeline capable of executing instructions out of program order, the pipeline having an instruction fetch portion and an instruction execution portion, wherein the instruction fetch portion of the pipeline transfers instructions to the instruction execution portion of the pipeline; and

pipeline control logic that

controls the instruction fetch portion of the pipeline to halt transferring instructions to the instruction execution portion of the pipeline when the instruction execution portion of the pipeline detects a misprediction associated with a control transfer instruction comprising a control transfer instruction ID checked by a misprediction instruction ID checker,

controls the instruction execution portion of the pipeline to continue executing instructions in the instruction execution portion of the pipeline when the misprediction is detected until the control transfer instruction reaches a selected stage in the instruction execution portion of the pipeline,

controls the instruction execution portion of the pipeline to invalidate instructions in the instruction execution portion of the pipeline once the control transfer instruction reaches the selected stage, and

controls the instruction fetch portion of the pipeline to restart transferring instructions to the instruction execution portion of the pipeline.

14. The processor of claim 13 , wherein the pipeline control logic controls the instruction execution portion of the pipeline to invalidate only instructions in the instruction execution portion of the pipeline associated with one of a plurality of program threads.

15. The processor of claim 13 , wherein the selected stage of the instruction execution portion of the pipeline is a stage prior to writing results generated by an arithmetic logic unit to a register file.

16. The processor of claim 13 , wherein the processor is capable of processing variable length instructions.