Apparatus and method for automatic low power mode invocation in a multi-threaded processor
View Patent ↗A processor comprises a processor core executing multiple threads. A bifurcated thread scheduler includes an internal processor core component and an external processor core component. The bifurcated thread scheduler identifies when all of the multiple threads are blocked and thereafter automatically enters a default low power sleep mode.
1. A processor, comprising:
a processor core executing multiple threads; and
a bifurcated thread scheduler including a scheduler component internal to the processor core and a policy manager component external to the processor core, wherein said bifurcated thread scheduler evaluates the execution state of said multiple threads against a variety of criteria to determine when all of said multiple threads are blocked and thereafter automatically enters a default low power sleep mode.
2. The processor of claim 1 wherein said bifurcated thread scheduler is configured to evaluate a criterion indicative of when a blocked thread is subject to a wait instruction.
3. The processor of claim 1 wherein said bifurcated thread scheduler is configured to evaluate a criterion indicative of when a blocked thread is subject to a yield instruction.
4. The processor of claim 1 wherein said bifurcated thread scheduler is configured to evaluate a criterion indicative of when a blocked thread is subject to a blocking inter-thread communication (ITC) access.
5. The processor of claim 1 wherein said bifurcated thread scheduler is configured to evaluate a criterion indicative of when a blocked thread is subject to a stopped priority request from said external processor core component.
6. The processor of claim 1 wherein said bifurcated thread scheduler is configured to enter said default low power sleep mode without issuing a wait instruction.
7. The processor of claim 1 wherein said processor is configured to perform housekeeping functions prior to entering said default low power sleep mode.
8. A computer readable storage medium, comprising executable instructions to:
define a processor core to execute multiple threads; and
specify a bifurcated thread scheduler including a scheduler component internal to the processor core and a policy manager component external to the processor core, wherein the bifurcated thread scheduler evaluates the execution state of said multiple threads against a variety of criteria to determine when all of the multiple threads are blocked and thereafter automatically enters a default low power sleep mode, wherein the processor core and the bifurcated thread scheduler are within a processor.