Processor utilizing a loop buffer to reduce power consumption
View Patent ↗The present invention provides processing systems, apparatuses, and methods that reduce power consumption with the use of a loop buffer. In an embodiment, an instruction fetch unit of a processor initially provides instructions from an instruction cache to an execution unit of the processor. While instructions are provided from the instruction cache to the execution unit, instructions forming a loop are stored in a loop buffer. When a loop stored in the loop buffer is being iterated, the instruction cache is disabled to reduce power consumption and instructions are provided to the execution unit from the loop buffer. When the loop is exited, the instruction cache is re-enabled and instructions are provided to the execution unit from the instruction cache.
1. A hardware processor, comprising:
an instruction source;
a loop buffer;
an instruction buffer; and
a controller;
the hardware processor being constructed and arranged such that if the controller identifies during instruction execution that a plurality of buffer instructions to be executed by the processor foams a loop, the controller:
stores the plurality of instructions that forms the loop in the loop buffer,
determines, based on a one of the plurality of instructions that forms the loop, whether a condition is true; and
modifies the operation of the instruction buffer based on the determined condition.
2. The processor of claim 1 , wherein the instruction source is a cache.
3. The processor of claim 1 , wherein the controller is configured to disable the instruction source following execution of one of a branch instruction and a jump instruction.
4. The processor of claim 3 , wherein the controller is configured to disable the instruction source after a preselected number of instructions have been stored in the loop buffer following execution of one of a branch instruction and a jump instruction.
5. The processor of claim 1 , wherein the controller is configured to enable the instruction source if an instruction to be executed by the processor is not available in the instruction buffer.
6. The processor of claim 1 , wherein the controller is configured to adjust a bias voltage applied to the instruction source, in response to the determined condition.
7. A method of fetching instructions in a processor having an instruction source, a loop buffer and an instruction buffer, comprising:
providing a plurality of instructions from the instruction source to the instruction buffer;
identifying during instruction execution, if a plurality of instructions from the instruction buffer forms a loop;
if the plurality of instructions forms a loop, storing the plurality of instructions from the instruction buffer in the loop buffer in response to the identifying;
disabling the instruction buffer when the plurality of instructions to be executed by the processor is available from the loop buffer.
8. A tangible computer readable storage medium comprising computer readable code defining a processor, the processor comprising:
an instruction source;
a loop buffer;
an instruction buffer configured to store instructions from the instruction source; and
a controller,
wherein, if the controller identifies during instruction execution that a plurality of instructions to be executed by the processor forms a loop, the controller stores the plurality of instructions in the loop buffer, and the controller selectively disables the instruction buffer when the plurality of instructions are available from the loop buffer.
9. The computer readable storage medium of claim 8 , wherein the controller stores the plurality of instructions in the loop buffer if the loop buffer comprises sufficient space to store the plurality of instructions.
10. The computer readable storage medium of claim 8 , wherein the computer-readable code comprises hardware description language code.
11. The computer readable storage medium of claim 10 , wherein the computer-readable program code is one of Verilog hardware description language code, VHDL hardware description language code, and SystemC hardware description language code.
12. A computer readable storage medium having encoded thereon computer program code for making or emulating a processor, the processor comprising:
an instruction source;
a loop buffer;
an instruction buffer configured to store instructions from the instruction source; and
a controller, wherein, if the controller identifies during instruction execution that a plurality of instructions to be executed by the processor forms a loop, the controller stores the plurality of instructions in the loop buffer, and the controller selectively disables the instruction buffer when the plurality of instructions are available from the loop buffer.
13. The hardware processor of claim 1 , wherein the controller selectively reduces the power consumption of the instruction buffer when the plurality of instructions is not available from the instruction buffer.
14. The method of claim 7 , further comprising:
selectively reducing the power consumption of the loop buffer when no loop is identified.
15. The tangible computer readable storage medium of claim 8 , wherein the controller selectively reduces the power consumption of the loop buffer when the plurality of instructions are not available from the instruction buffer.
16. The computer readable storage medium of claim 12 , wherein the controller selectively reduces the power consumption of the loop buffer when the plurality of instructions is not available from the instruction buffer.
17. A processor, comprising:
a first buffer configured to store instructions, and to selectively provide instructions to an execution unit of the processor for execution;
a second buffer configured to store instructions provided from the first buffer, and to selectively provide instructions to the execution unit for execution, wherein if a plurality of instructions from the first buffer is determined to form a loop, the plurality of instructions is provided to the second buffer; and
a controller configured to:
control whether instructions are provided to the execution unit from the first buffer or the second buffer;
determine during program execution that a program control instruction that directs transfer of program control to a target instruction has been taken or is predicted to be taken;
make a determination during program execution that the target instruction is present in the second buffer; wherein upon a determination that the target instruction is present in the second buffer, cause the second buffer to provide instructions to the execution unit and disable the first instruction buffer; and
turn off the second buffer when the target instruction is not present in the second buffer.
18. The processor of claim 17 , wherein the controller is further configured to reduce a power consumption of at least one of the first buffer or the second buffer, respectively, when instructions are not being provided from the respective buffer.
19. The hardware processor of claim 1 , wherein the modification of the instruction buffer comprises disabling the instruction buffer.
20. The hardware processor of claim 1 , wherein the controller modifies the operation of the instruction buffer for as long as the loop is in the loop buffer.
21. The hardware processor of claim 1 , wherein the condition corresponds to the loop exiting.