Configurable co-processor interface
View Patent ↗A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.
1. An interface between a central processing unit (CPU) and a plurality of coprocessors for transferring data from the CPU to one of the plurality of coprocessors, comprising:
a first set of interconnects configured to transfer a first data instruction and a second data instruction from the CPU to the one of the plurality of coprocessors simultaneously;
a second set of interconnects configured to tranfer data, associated with said first and said second data instructions, out-of-order; and
a third set of interconnects configured to indicate to the one of the plurality of coprocessors a relative data order for execution of said first and said second data instructions.
2. The interface as recited in claim 1 , wherein said data is transferred to the one of the plurality of coprocessors without any tag information which would otherwise relate said data with said first and said second data instructions.
3. The interface as recited in claim 1 , wherein said first set of interconnects comprises:
data signal interconnects configured to dispatch said data from the CPU; and
a TO coprocessor data strobe interconnect configured to signal transfer of said data to the one of the plurality of coprocessors.
4. The interface of claim 1 , wherein the first and second data instructions belong to a first data instruction group, and wherein the interface further comprises:
a fourth set of interconnects configured to transfer a third data instruction and a fourth data instruction from the CPU to the one of the plurality of coprocessors simultaneously,
wherein the third and fourth data instructions belong to a second data instruction group.
5. A data transfer interface between a central processing unit (CPU) and a plurality of coprocessors for transferring data to one of the plurality of coprocessors, comprising:
a first set of interconnects configured to transfer a first data instruction and a second data instruction from the CPU to the one of the plurality of coprocessors simultaneously;
a second set of interconnects configured to transfer M sets of data from the CPU to the one of the plurality of coprocessors, out-of-order; and
a third set of interconnects configured to convey distinct signals to indicate to the one of the plurality of coprocessors a relative data order for execution of said first and said second data instructions.
6. The data transfer interface as recited in claim 5 , wherein said third set of interconnects comprises a plurality of interconnects configured to convey distinct signals of the relative order of execution.
7. The data transfer interface as recited in claim 5 , wherein said first set of interconnects is also configured to transfer M data instructions from the one of the plurality of coprocessors to the CPU and said second set of interconnects is also configured to transfer M sets of data from the one of the plurality of coprocessors to the CPU.
8. The data transfer interface of claim 5 , wherein the first and second data instructions belong to a first data instruction group, and wherein the data transfer interface further comprises:
a fourth set of interconnects configured to transfer a third data instruction and a fourth data instruction from the CPU to the one of the plurality of coprocessors simultaneously,
wherein the third and fourth data instructions belong to a second data instruction group.
9. A method for transferring instructions, and data associated with the instructions, from a central processing unit (CPU) to one of a plurality of coprocessors, where the data associated with the instructions is transferred in variable time slots after transfer of their associated instructions, and out-of-order with respect to their associated instructions, the method comprising:
transferring a first data instruction and a second data instruction to the one of the plurality of coprocessors simultaneously; and
providing, along with the transferring, a relative data order indication for execution of said first and said second data instructions.
10. The method of claim 9 , wherein the first and second data instructions belong to a first instruction group, and wherein the method further comprises:
transferring a third instruction and a fourth instruction to the one of the plurality of coprocessors simultaneously,
wherein the third and fourth instructions belong to a second instruction group.