Trace control block implementation and method
View Patent ↗A system and method for program counter and data tracing is disclosed. A trace interface is provided for communication of trace information between a processor core and a trace control block. The trace interface enables various combinations of processor cores and trace control blocks to be implemented.
1. A tracing system, comprising:
a processor core; and
trace generation logic coupled to said processor core, said trace generation logic having a trace interface that enables transmission of trace information that is generated based on execution of instructions in said processor core, said trace generation logic including a first-in-first-out (FIFO) buffer that stores trace information prior to transmission on said trace interface;
wherein said trace interface further includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.
2. A tracing system, comprising:
a processor core; and
trace generation logic coupled to said processor core, said trace generation logic having a trace interface that enables transmission of trace information that is generated based on execution of instructions in said processor core, said trace generation logic including a first-in-first-out (FIFO) buffer that stores trace information prior to transmission on said trace interface;
wherein said trace interface includes an instruction completion status signal, a data bus signal, and a transmission type signal that identifies data transmitted via said data bus signal;
wherein said trace interface further includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.
3. The tracing system of claim 2 , further comprising a trace capture component configured to operate with said trace interface to thereby receive trace information.
4. The tracing system of claim 3 , wherein said trace capture component is implemented on a common substrate with said processor core and said trace generation logic.
5. The tracing system of claim 2 , wherein said trace interface further includes a load order signal that identifies an out-of-order position of load data.
6. The tracing system of claim 2 , wherein said processor core includes multiple instruction pipelines, wherein said trace interface further includes a program order signal that identifies a static program schedule of an instruction.
7. The tracing system of claim 2 , wherein said trace interface includes an overflow signal that indicates an overflow condition in said FIFO buffer.
8. The tracing system of claim 2 , wherein said trace interface includes control signals that control operation of said trace generation logic.
9. A computer program product comprising:
computer-readable program code for causing a computer to describe a processor core;
computer-readable program code for causing a computer to describe a trace generation logic coupled to said processor core, said trace generation logic having a trace interface that enables transmission of trace information that is generated based on execution of instructions in said processor core, said trace generation logic including a first-in-first-out (FIFO) buffer that stores trace information prior to transmission on said trace interface;
wherein said trace interface includes an instruction completion status signal, a data bus signal, and a transmission type signal that identifies data transmitted via said data bus signal;
wherein said trace interface further includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus; and
a computer-usable medium configured to store the computer-readable program codes.
10. A method for enabling a computer to generate tracing logic, comprising:
transmitting computer-readable program code over the Internet to a computer, said computer-readable program code including:
computer-readable program code for causing a computer to describe a processor core; and
computer-readable program code for causing a computer to describe a trace generation logic coupled to said processor core, said trace generation logic having a trace interface that enables transmission of trace information that is generated based on execution of instructions in said processor core, said trace generation logic including a first-in-first-out (FIFO) buffer that stores trace information prior to transmission on said trace interface;
wherein said trace interface includes an instruction completion status signal, a data bus signal, and a transmission type signal that identifies data transmitted via said data bus signal;
wherein said trace interface further includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus;
whereby said transmitting computer-readable program code enables a destination computer to read said computer-readable program code and describe said processor core and said trace generation logic.
11. A computer-readable medium storing computer-readable program code, comprising:
computer-readable program code for causing a computer to describe a processor core; and
computer-readable program code for causing a computer to describe a trace generation logic coupled to said processor core, said trace generation logic having a trace interface that enables transmission of trace information that is generated based on execution of instructions in said processor core, said trace generation logic including a first-in-first-out (FIFO) buffer that stores trace information prior to transmission on said trace interface;
wherein said trace interface includes an instruction completion status signal, a data bus signal, and a transmission type signal that identifies data transmitted via said data bus signal;
wherein said trace interface further includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.
12. A trace capture system, comprising:
an interface component, said interface component being defined to support a specified trace interface, said interface component enabling said trace capture system to communicate with trace generation logic, coupled to a processor core, that supports said specified trace interface; and
a trace memory format component that assembles trace information received via said specified trace interface into a format for storage in trace memory;
wherein said specified trace interface includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.
13. A trace capture system, comprising:
an interface component, said interface component being defined to support a specified trace interface, said interface component enabling said trace capture system to communicate with trace generation logic, coupled to a processor core, that supports said specified trace interface; and
a trace memory format component that assembles trace information received via said specified trace interface into a format for storage in trace memory;
wherein said specified trace interface includes an instruction completion status signal, a data bus signal, and a transmission type signal that identifies data transmitted via said data bus signal;
wherein said specified trace interface further includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.
14. The trace capture system of claim 13 , wherein said specified trace interface further includes a load order signal that identifies an out-of-order position of load data.
15. The trace capture system of claim 13 , wherein said specified trace interface further includes a program order signal that identifies a static program schedule of an instruction completed by one of a plurality of instruction pipelines in a processor core.
16. The trace capture system of claim 13 , wherein said specified trace interface includes an overflow signal that indicates an overflow condition in a first-in-first-out buffer in a trace generation logic coupled to said trace capture system.
17. The trace capture system of claim 13 , wherein said trace interface includes control signals that control operation of a trace generation logic coupled to said trace capture system.
18. A computer program product comprising:
computer-readable program code for causing a computer to describe an interface component, said interface component being defined to support a specified trace interface, said interface component enabling said trace capture system to communicate with trace generation logic, coupled to a processor core, that supports said specified trace interface;
computer-readable program code for causing a computer to describe a trace memory format component that assembles trace information received via said specified trace interface into a format for storage in trace memory; and
a computer-usable medium configured to store the computer-readable program codes;
wherein said specified trace interface includes an instruction completion status signal, a data bus signal, and a transmission type signal that identifies data transmitted via said data bus signal;
wherein said specified trace interface further includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.
19. A method for enabling a computer to generate logic, comprising:
transmitting computer-readable program code over the Internet to a computer, said computer-readable program code including:
computer-readable program code for causing a computer to describe an interface component, said interface component being defined to support a specified trace interface, said interface component enabling said trace capture system to communicate with trace generation logic, coupled to a processor core, that supports said specified trace interface; and
computer-readable program code for causing a computer to describe a trace memory format component that assembles trace information received via said specified trace interface into a format for storage in trace memory;
wherein said specified trace interface includes an instruction completion status signal, a data bus signal, and a transmission type signal that identifies data transmitted via said data bus signal;
wherein said specified trace interface further includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus;
whereby said transmitting computer-readable program code enables a destination computer to read said computer-readable program code and describe said interface component and said trace memory format component.
20. A computer-readable medium storing computer-readable program code, comprising:
computer-readable program code for causing a computer to describe an interface component, said interface component being defined to support a specified trace interface, said interface component enabling said trace capture system to communicate with trace generation logic, coupled to a processor core, that supports said specified trace interface; and
computer-readable program code for causing a computer to describe a trace memory format component that assembles trace information received via said specified trace interface into a format for storage in trace memory;
wherein said trace interface includes an instruction completion status signal, a data bus signal, and a transmission type signal that identifies data transmitted via said data bus signal;
wherein said specified trace interface further includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.
21. A tracing system, comprising:
a processor core; and
trace generation logic coupled to said processor core, said trace generation logic having a trace interface that enables transmission of trace information that is generated based on execution of instructions in said processor core, wherein support of said trace interface by said trace generation logic enables said trace generation logic to be combined with a trace capture component that is designed to support said trace interface;
wherein said trace interface further includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.
22. A computer program product comprising:
computer-readable program code for causing a computer to describe a processor core;
computer-readable program code for causing a computer to describe a trace generation logic coupled to said processor core, said trace generation logic having a trace interface that enables transmission of trace information that is generated based on execution of instructions in said processor core, said trace generation logic including a first-in-first-out (FIFO) buffer that stores trace information prior to transmission on said trace interface wherein said trace interface includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus; and
a computer-usable medium configured to store the computer-readable program codes.
23. A computer-readable medium storing computer-readable program code, comprising:
computer-readable program code for causing a computer to describe a processor core; and
computer-readable program code for causing a computer to describe a trace generation logic coupled to said processor core, said trace generation logic having a trace interface that enables transmission of trace information that is generated based on execution of instructions in said processor core, said trace generation logic including a first-in-first-out (FIFO) buffer that stores trace information prior to transmission on said trace interface wherein said trace interface includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.
24. A computer-readable medium comprising:
computer-readable program code for causing a computer to describe a processor core; and
computer-readable program code for causing a computer to describe a trace generation logic coupled to said processor core, said trace generation logic having a trace interface that enables transmission of trace information that is generated based on execution of instructions in said processor core, said trace generation logic including a first-in-first-out (FIFO) buffer that stores trace information prior to transmission on said trace interface;
wherein said trace interface includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.
25. A computer program product comprising:
computer-readable program code for causing a computer to describe an interface component, said interface component being defined to support a specified trace interface, said interface component enabling said trace capture system to communicate with trace generation logic, coupled to a processor core, that supports said specified trace interface;
computer-readable program code for causing a computer to describe a trace memory format component that assembles trace information received via said specified trace interface into a format for storage in trace memory; and
a computer-usable medium configured to store the computer-readable program codes wherein said specified trace interface includes a transmission, end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.
26. A computer-readable medium, comprising:
computer-readable program code for causing a computer to describe an interface component, said interface component being defined to support a specified trace interface, said interface component enabling said trace capture system to communicate with trace generation logic, coupled to a processor core, that supports said specified trace interface; and;
computer-readable program code for causing a computer to describe a trace memory format component that assembles trace information received via said specified trace interface into a format for storage in trace memory wherein said specified trace interface includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.
27. A computer-readable medium comprising:
computer-readable program code for causing a computer to describe an interface component, said interface component being defined to support a specified trace interface, said interface component enabling said trace capture system to communicate with trace generation logic, coupled to a processor core, that supports said specified trace interface; and
computer-readable program code for causing a computer to describe a trace memory format component that assembles trace information received via said specified trace interface into a format for storage in trace memory
wherein said specified trace interface includes a transmission end signal that identifies a last cycle of a transmission on said data bus, and a transmission mode signal that identifies a mode of transmission on said data bus.