IP Library › Granted Patent US 7,533,219
Granted Patent B2
US 7,533,219 · App. 11/272,719 · Granted May 12, 2009

Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme

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Quick Facts
Patent No.
US 7,533,219
App. No.
11/272,719
Granted
May 12, 2009
Kind
B2
Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2014
From: BRIDGE CROSSING, LLC
To: ARM FINANCE OVERSEAS LIMITED
Reel/Frame 033074/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2013
From: MIPS TECHNOLOGIES, INC.
To: BRIDGE CROSSING, LLC
Reel/Frame 030202/0440 →