IP Library Granted Patent US 7,039,060
Granted Patent B2
US 7,039,060 · App. 09/799,610 · Granted May 2, 2006

System and method for extracting fields from packets having fields spread over more than one register

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,039,060
App. No.
09/799,610
Granted
May 2, 2006
Kind
B2
Abstract

Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction extracting any part of the field from a second general register designated as a second source register. The second instruction inserts any extracted field parts in a result register.

Claims (90)

1. A processing system for extracting a field from a packet, said system comprising:

an instruction memory having a pair of instructions;

a processor having a set of general registers, at least a portion of said packet being stored in a pair of general registers, said processor being configured to

extract, responsive to a first one of the instructions, any part of said field in a first one of the pair of general registers designated as a first source register, and

extract, responsive to a second one of the instructions, any part of said field in a second one of the pair of general registers designated as a second source register

store any extracted part of the field extracted from the first source register in a temporary result register; and

insert, responsive to the second instruction, any portion of the field extracted from the second one of the general registers, along with any part of the field in the temporary result register, into a final result register.

2. The system of claim 1 , said processor being further configured to:

extract additional fields from the packet;

insert a value contained in the additional fields in the final result register; and

access a table lookup unit using the value in the final result register as a key.

3. The system of claim 1 , said processor being further configured to:

parse the packet to determine a packet formal.

4. The system of claim 3 , said processor being further configured to:

determine field information for the field to be extracted based on the packet format, wherein said field information includes a width of the field and an extraction offset indicating a position of the field in the packet.

5. The system of claim 4 , said processor being further configured to:

determine whether the field to be extracted is stored entirely within the first source register.

6. The system of claim 4 , said processor being further configured to:

determine that the field to be extracted is stored entirely within the first source register when an extraction offset is less than n bits and a sum of the extraction offset and the width minus one is less than n bits, where n is a width of the first source register.

7. The system of claim 4 , said processor being further configured to:

determine whether the field to be extracted is partly in the first source register.

8. The system of claim 4 , said processor being further configured to:

determine that the field to be extracted is partly in the first source register when an extraction offset is less than n bits and a sum of the extraction offset and the width minus one is greater than n minus one bits, where n is the width of the first source register.

9. The system of claim 4 , said processor being further configured to:

determine whether the field to be extracted is absent from the source register.

10. The system of claim 4 , said processor being further configured to:

determine that the field to be extracted is absent from the source register when the extraction offset is greater than n minus one bits, where n is the width of the source register.

11. The system of claim 4 , said processor being further configured to:

determine whether the field to be extracted is entirely held in the second source register.

12. The system of claim 4 , said processor being further configured to:

determine that the field to be extracted is entirely held in the second source register when the extraction offset is greater than n minus one bits, where n is the width of the second source register.

13. The system of claim 11 , said processor being further configured to:

extract the field from the second source register and store the result in the final result register when the field to be extracted is entirely held in the second source register.

14. The system of claim 4 , said processor being further configured to:

determine whether the field is partially in the second source register.

15. The system of claim 4 , said processor being further configured to:

determine that the field is partially in the second source register when the extraction offset is less than n bits and the sum of the extract offset and the width minus one is greater than n minus one bits, where n is the width of the second source register.

16. The system of claim 14 wherein the field information includes an insertion offset, said processor being further configured to:

extract, when the field is partially in the second register, the portion of the field in the second source register and inserting the result, along with the part of the field extracted by the first instruction, into a final result register offset by the insertion offset.

17. The system of claim 4 , said processor being further configured to:

determine whether the field is absent from the second source register.

18. The system of claim 4 , said processor being further configured to:

determine that the field is absent from the second source register when an extraction offset is less than n bits and the sum of the extraction offset and the width minus one is less than n bits, where n is the width of the source register.

19. The system of claim 17 , said processor being further configured to:

copy a field extracted by the first instruction to a final result register when the field is absent from the second source register.

20. A method for extracting a field from a packet comprising:

storing at least a portion of the packet in a pair of general registers;

executing a first instruction extracting any part of the field from a first one of the pair of general registers designated as a first source register;

executing a second instruction extracting any part of the field from a second one of the pair of general registers designated as a second source register; and

storing any extracted part of the field extracted from the first source register in a temporary result register, wherein said step of executing a second instruction includes the step of inserting any portion of the field extracted from the second one of the general registers, along with any part of the field in the temporary result register, into a final result register.

21. The method of claim 20 further including:

extracting additional fields from the packet and inserting a value contained in the additional fields in the final result register.

22. The method of claim 21 further including:

accessing a table lookup unit using the value in the final result register as a key.

23. The method of claim 20 further including:

parsing the packet to determine a packet format.

24. The method of claim 23 further including:

determining field information for the field to be extracted based on the packet format, wherein said field information includes a size of the field and an extraction offset indicating a position of the field in the packet.

25. The method of claim 24 wherein executing a first instruction includes:

determining whether the field to be extracted is stored entirely within the first source register.

26. The method of claim 25 wherein determining further includes:

determining whether an extraction offset is less than n bits and a sum of the extraction offset and a width minus one is less than n bits, where n is the width of the first source register.

27. The method of claim 24 wherein executing a first instruction includes:

determining whether the field of interest is partly in the first source register.

28. The method of claim 27 wherein said determining further includes:

determining whether an extraction offset is less than n bits and a sum of the extraction offset and a width minus one is greater than n minus one bits, where n is the width of the first source register.

29. The method of claim 24 wherein executing a first instruction includes:

determining whether the field of interest is absent from the source register.

30. The method of claim 29 wherein said determining further includes:

determining whether the extraction offset is greater than n minus one bits, where n is the width of the source register.

31. The method of claim 24 wherein said executing a second instruction includes:

determining whether the field to be extracted is entirely held in the second source register.

32. The method of claim 31 wherein said determining includes:

determining whether the extraction offset is greater than n minus one bits, where n is the width of the second source register.

33. The method of claim 31 further including:

extracting the field from the second source register; and

storing the result in the final result register when the field to be extracted is entirely held in the second source register.

34. The method of claim 24 wherein said executing a second instruction includes:

determining whether the field is partially in the second source register.

35. The method of claim 34 wherein determining includes:

determining whether the extraction offset is less than n bits and the sum of the extract offset and a width minus one is greater than n minus one bits, where n is the width of the second source register.

36. The method of claim 34 wherein the field information includes an insertion offset, said method further including:

extracting, when the field is partially in the second register, the portion of the field in the second source register; and

inserting the result, along with the part of the field extracted by the first instruction, into a final result register offset by the insertion offset.

37. The method of claim 24 wherein executing a second instruction includes:

determining whether the field is absent from the second source register.

38. The method of claim 37 wherein determining includes:

determining whether an extraction offset is less than n bits and the sum of the extraction offset and the width minus one is less than n bits, where n is the width of the second source register.

39. The method of claim 37 further including:

copying a field extracted by the first instruction to a final result register when the field is absent from the second source register.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2014
From: BRIDGE CROSSING, LLC
To: ARM FINANCE OVERSEAS LIMITED
Reel/Frame 033074/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2013
From: MIPS TECHNOLOGIES, INC.
To: BRIDGE CROSSING, LLC
Reel/Frame 030202/0440 →
RELEASE OF SECURITY INTEREST Recorded Dec 16, 2008
From: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
To: MIPS TECHNOLOGIES, INC.
Reel/Frame 021985/0015 →
SECURITY AGREEMENT Recorded Aug 24, 2007
From: MIPS TECHNOLOGIES, INC.
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 019744/0001 →
CORRECTIVE DOCUMENT REEL/FRAME 012170/0295 Recorded Oct 20, 2005
From: GELINAS, ROBERT; HAYS, W. PATRICK; KATZMAN, SOL
To: LEXRA, INC.
Reel/Frame 017112/0794 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2002
From: LEXRA, INC.
To: MIPS TECHNOLOGIES, INC.
Reel/Frame 013174/0315 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2002
From: KATZMAN, SOL; GELINAS, ROBERT; HAYS, W. PATRICK
To: LEXRA, INC.
Reel/Frame 013174/0322 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2001
From: KATZMAN, SOL; GELINAS, ROBERT; HAYS, W. PATRICK
To: LEXRA COMPUTING ENGINES
Reel/Frame 012170/0295 →