Providing extended precision in SIMD vector arithmetic operations
View Patent ↗The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.
1. A computer-based method for providing extended precision in single instruction multiple data (SIMD) arithmetic operations, comprising:
(a) loading a first vector into a first register, the first vector comprising a plurality of N-bit elements;
(b) loading a second vector into a second register, the second vector comprising a plurality of N-bit elements;
(c) executing an arithmetic instruction for at least one pair consisting of an N-bit element in the first register and an N-bit element in the second register, to produce a resulting element;
(d) writing the resulting element into an M-bit element of an accumulator, wherein M is greater than N;
(e) transforming the resulting element into a width of N-bits; and
(f) writing the resulting element into a third register;
wherein a plurality of M-bit resulting elements in the accumulator are wrapped around the representable range of the resulting elements.
2. The method as recited in claim 1 , wherein M is greater than 2N.
3. The method as recited in claim 1 , wherein the transforming comprises clamping the resulting element.
4. The method as recited in claim 3 , further comprising rounding the resulting element.
5. The method as recited in claim 4 , further comprising shifting the resulting element.
6. The method as recited in claim 4 , wherein the rounding comprises one of:
rounding the resulting element towards zero;
rounding the resulting element towards the nearest unit, wherein the resulting element is rounded away from zero if the resulting element is at least halfway towards the nearest unit; and
rounding the resulting element towards the nearest unit, wherein the resulting element is rounded towards zero if the resulting element is at least halfway towards the nearest unit.
7. The method as recited in claim 1 , wherein the transforming comprises rounding the resulting element.
8. The method as recited in claim 7 , further comprising shifting the resulting element.
9. The method as recited in claim 7 , wherein the rounding comprises one of:
rounding the resulting element towards zero;
rounding the resulting element towards the nearest unit, wherein the resulting element is rounded away from zero if the resulting element is at least halfway towards the nearest unit; and
rounding the resulting element towards the nearest unit, wherein the resulting element is rounded towards zero if the resulting element is at least halfway towards the nearest unit.
10. A processor for providing extended precision in single instruction multiple data (SIMD) arithmetic operations, comprising:
means for executing an arithmetic instruction involving an element of a first vector and an element of a second vector to produce a resulting element, the first and second vectors comprising a plurality of N-bit elements;
an accumulator for receiving the resulting element, wherein the resulting element is stored in an M-bit element of the accumulator and wherein M is greater than N;
means for transforming the resulting element into a width of N-bits; and
means for writing the transformed resulting element to a register;
wherein a plurality of M-bit resulting elements in the accumulator are wrapped around the representable range of the resulting elements.
11. The processor as recited in claim 10 , wherein the means for transforming comprises:
means for shifting the resulting element for scaling the value of the resulting element;
means for rounding the resulting element; and
means for clamping the resulting element.
12. The processor as recited in claim 10 , wherein M is greater than 2N.
13. The processor as recited in claim 10 , wherein the means for transforming comprises means for clamping the resulting element.
14. The processor as recited in claim 13 , wherein the means for transforming further comprises means for rounding the resulting element.
15. The processor as recited in claim 14 , wherein the means for transforming further comprises means for shifting the resulting element.
16. The processor as recited in claim 14 , wherein the rounding means comprises one of:
means for rounding the resulting element towards zero;
means for rounding the resulting element towards the nearest unit, wherein the resulting element is rounded away from zero if the resulting element is at least halfway towards the nearest unit; and
means for rounding the resulting element towards the nearest unit, wherein the resulting element is rounded towards zero if the resulting element is at least halfway towards the nearest unit.
17. A computer-based method for providing extended precision in single instruction multiple data (SIMD) arithmetic operations, comprising:
(a) loading a first vector into a first register, the first vector comprising a plurality of N-bit elements;
(b) loading a second vector into a second register, the second vector comprising a plurality of N-bit elements;
(c) executing an arithmetic instruction for at least one pair consisting of an N-bit element in the first register and an N-bit element in the second register, to produce a resulting element;
(d) writing the resulting element into an M-bit element of an accumulator, wherein M is greater than N;
(e) rounding the resulting element to a width of N-bits, wherein the rounding comprises one of:
rounding the resulting element towards the nearest unit, wherein the resulting element is rounded away from zero if the resulting element is at least halfway towards the nearest unit; and
rounding the resulting element towards the nearest unit, wherein the resulting element is rounded towards zero if the resulting element is at least halfway towards the nearest unit; and
(f) writing the rounded resulting element into a third register.
18. The method as recited in claim 17 , further comprising shifting the resulting element.
19. The method as recited in claim 17 , further comprising clamping the resulting element.
20. The method as recited in claim 17 , wherein M is greater than 2N.