Processor core and multiplier that support both vector and single value multiplication

1. A processor core to execute an instruction to perform both vector and single value multiplication, comprising:

a plurality of general purpose registers;

an accumulation register; and

an execution unit, coupled to the general purpose registers and the accumulation register that includes:

a partial product generator that generates a plurality of first partial products and a plurality of second partial products given a first input and a second input,

a first adder array, coupled to the partial product generator, that generates a first result for the plurality of first partial products;

a second adder array, configured in parallel with the first adder array, coupled to the partial product generator, that generates a second result for the plurality of second partial products; and

a combiner, coupled to the first adder array and the second adder array, that generates a final result based on the first result and the second result, wherein

if the first input and the second input represent single values, the partial product generator assigns a value of zero only to either a most significant partial product of the plurality of second partial products or to a least significant partial product of the plurality of first partial products.

2. The processor core of claim 1 , wherein the partial product generator comprises:

a recoder, and

a partial product generator, coupled to the recoder,

wherein if the first input and the second input represent vectors, the partial product generator generates the first partial products based on the first value of the first input, the first value of the second input and recoding, and generates the second partial products based on the second value of the first input, the second value of the second input and recoding.

3. The processor core of claim 1 , wherein the first adder array and the second adder array comprise carry-save adders and the first result and the second result each contain a carry and a save, the combiner comprising:

a first adder, coupled to the first adder array, that generates a third result based on the carry and the save of the first result; and

a second adder, coupled to the second adder array, that generates a fourth result based on the carry and the save of the second result,

wherein the third result and the fourth result are combined to generate the final result and stored in a first general purpose register.

4. The processor core of claim 1 , wherein the combiner comprises:

a shift unit, coupled to the first adder array and the second adder array,

wherein if the first input and the second input each contain a fractional value, the shift unit shifts the first result and the second result by at least one bit.

5. The processor core of claim 4 , wherein if the first input and the second input represent vectors, the shift unit shifts the second result so that the second result has the same bit significance as the first result.

6. The processor core of claim 4 , wherein the combiner further comprises:

a saturation unit, coupled to the shift unit, wherein

if the first input and the second input represent single values each equal to negative one, the saturation unit replaces the first result with a first saturation result and the second result with a second saturation result,

if the first input and the second input represent vectors and the first value of the first input and the first value of the second input each equal negative one, the saturation unit replaces the first result with a third saturation result, and

if the first input and the second input represent vectors and the second value of the first input and the second value of the second input each equal negative one, the saturation unit replaces the second result with a fourth saturation result.

7. The processor core of claim 6 , wherein the combiner further comprises:

a third adder array, coupled to the saturation unit, generate the final result based on the first result, the second result, and a value stored in the accumulation register, the final result being stored in the accumulation register.

8. The processor core of claim 7 , wherein the execution unit implements a multiply and accumulate instruction, wherein the first input and the second input are received from the general purpose registers, an accumulation value is received from the accumulation register and the final result is stored in the accumulation register.

9. The processor core of claim 7 , wherein the execution unit implements a multiply, add, and accumulate instruction, wherein the first input and the second input are received from the general purpose registers, an accumulation value is received from the accumulation register and the final result is stored in the accumulation register.

10. The processor core of claim 7 , wherein the execution unit implements a multiply vector instruction, wherein the first input and the second input are received from the general purpose registers and the final result is stored in one of the general purpose registers.

11. A computer readable storage medium having embodied thereon computer readable program code to generate a processor to perform a multiplication, the computer readable program code comprising:

first computer readable program code to generate a partial product generator that generates a plurality of first partial products and a plurality of second partial products given a first input and a second input, wherein the plurality of first partial products has a higher bit significance than the plurality of second partial products;

second computer readable program code to generate a first adder array, coupled to the partial product generator, that generates a first result for plurality of first partial products;

third computer readable program code to generate a second adder array, configured in parallel with the first adder array, coupled to the partial product generator, a second result for the plurality of second partial products; and

fourth computer readable program code to generate a combiner, coupled to the first adder array and the second adder array, that generates a final result based on the first result and the second result, wherein

if the first input and the second input represent single values, the partial product generator assigns a value of zero only to either a most significant partial product of the plurality of second partial products or to a least significant partial product of the plurality of first partial products.

12. The computer readable storage medium of claim 11 , wherein the first computer program code for the partial product generator comprises:

fifth computer program code to generate a recoder, and

sixth computer program code to generate a partial product selector, coupled to the recoder,

wherein if the first input and the second input represent vectors, the partial product selector generates the first partial products based on the first value of the first input, the first value of the second input and recoding, and generates the second partial products based on the second value of the first input, the second value of the second input and recoding.

13. The computer readable storage medium of claim 11 , wherein the second and third computer program code for the first adder array and the second adder array comprise carry-save adders and the first result and the second result each contain a carry and a save, the fourth computer program code for the combiner comprising:

fifth computer program code to generate a first adder, coupled to the first adder array, that generates a third result based on the carry and the save of the first result; and

sixth computer program code to generate a second adder, coupled to the second adder array, that generates a fourth result based on the carry and the save of the second result,

wherein the third result and the fourth result are combined to generate the final result.

14. The computer readable storage medium of claim 11 , wherein the fourth computer program code for the combiner comprises:

fifth computer program code to generate a shift unit, coupled to the first adder array and the second adder array,

wherein if the first input and the second input each contain a fractional value, the shift unit shifts the first result and the second result by at least one bit.

15. The computer readable storage medium of claim 14 , wherein if the first input and the second input represent vectors, the fifth computer program code for the shift unit shifts the second result so that the second result has the same bit significance as the first result.

16. The computer readable storage medium program code of claim 14 , wherein the fourth computer program code for the combiner further comprises:

fifth computer program code to generate a saturation unit, coupled to the shift unit, wherein

if the first input and the second input represent single values each equal to negative one, the saturation unit replaces the first result with a first saturation result and the second result with a second saturation result,

if the first input and the second input represent vectors and the first value of the first input and the first value of the second input each equal negative one, the saturation unit replaces the first result with a third saturation result, and

if the first input and the second input represent vectors and the second value of the first input and the second value of the second input each equal negative one, the saturation unit replaces the second result with a fourth saturation result.

17. The computer readable storage medium of claim 16 , wherein the fourth computer program code for the combiner further comprises:

fifth computer program code for a third adder array, coupled to the saturation unit, that generates the final result based on the first result, the second result, and an accumulation value.

18. A multiplier in a hardware processor that supports both vector and single value multiplication in response to an instruction, comprising:

a partial product generator that generates a plurality of first partial products and a plurality of second partial products given a first input and a second input, wherein the plurality of first partial products has a higher bit significance than the plurality of second partial products;

a first adder array, coupled to the partial product generator, that generates a first result for the plurality of first partial products;

a second adder array, configured in parallel with the first adder array, coupled to the partial product generator, that generates a second result for the plurality of second partial products; and

a combiner, coupled to the first adder array and the second adder array, that generates a final result based on the first result and the second result, wherein

if the first input and the second input represent single values, the partial product generator assigns a value of zero only to either a most significant partial product of the plurality of second partial products or to a least significant partial product of the plurality of first partial products.

19. A multiplication method of executing an instruction to perform both vector and single value multiplication, comprising:

receiving a first input and a second input wherein the first input and the second input each represent one of a single value and a vector;

producing a plurality of first partial products, using a Booth recoder, and a plurality of second partial products based on the first input and the second input, wherein the plurality of first partial products has a higher bit significance than the plurality of second partial products, wherein

if the first input and the second input represent single values, only either a most significant partial product of the plurality of second partial products or a least significant partial product of the plurality of first partial products is assigned the value of zero;

adding, using a first adder array, the plurality of first partial products to generate a first result;

adding, using a second adder array, configured in parallel with the first adder array, the plurality of second partial products to generate a second result; and

combining, using a combiner coupled to the first and second adder array, the first result and the second result to generate a final result.

20. A processor multiplier to execute an instruction to perform both vector and single value multiplication, comprising:

a partial product generator that generates a plurality of first partial products and a plurality of second partial products given a first input and a second input;

a first adder array, coupled to the partial product generator, that generates a first result for the plurality of first partial products;

a second adder array, configured in parallel with the first adder array, coupled to the partial product generator, that generates a second result for the plurality of second partial products, the second adder array accepting an additional partial product directly from the partial product generator; and

a combiner, coupled to the first adder array and the second adder array, that generates a final result based on the first result and the second result,

wherein if the first input and the second input represent single values, the partial product generator assigns a value of zero only to either a most significant partial product of the plurality of second partial products or to a least significant partial product of the plurality of first partial products, and

wherein a significance of the most significant partial product of the plurality of second partial products is equal to a significance of the least significant partial product of the plurality of first partial products.

21. The processor multiplier of claim 20 , wherein the first input and second input represent vectors each containing two values, the values in the first input are represented with more bits than the values in the second input, and wherein the values in the first input are used as the multiplicand.

22. The processor core of claim 1 , wherein a significance of the most significant partial product of the plurality of second partial products is equal to a significance of the least significant partial product of the plurality of first partial products.