High performance RISC instruction set digital signal processor having circular buffer and looping controls
View Patent ↗A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seem less transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular buffer support, an interruptible and nested zero-overhead loop counter, and prioritized low-overhead interrupts.
1. A circular buffer control circuit, comprising
a first number of circular buffer start registers;
a first number of circular buffer end registers, each associated with a different one of the circular buffer start registers; and
circular buffer control logic including
means for comparing a pointer to a first address stored in a selected one of the circular buffer end registers, and
means for restoring to a register file a second address stored in the one of the circular buffer start registers associated with the selected circular buffer end register, if the pointer matches the first address stored in the selected circular buffer end register.
2. The circular buffer control circuit of claim 1 , wherein the circular buffer control logic further includes
means for modifying the pointer by a stride value.
3. The circular buffer control circuit of claim 2 , wherein the stride value is programmable.
4. A circular buffer control circuit, comprising
a first number of circular buffer start registers;
a first number of circular buffer end registers, each associated with a different one of the circular buffer start registers; and
control logic that compares a pointer to a first address stored in a selected one of the circular buffer end registers and restores to a register file a second address stored in the one of the circular buffer start registers associated with the selected circular buffer end register, if the pointer matches the first address stored in the selected circular buffer end register.
5. The circular buffer control circuit of claim 4 , wherein the control logic modifies the pointer by a stride value.
6. The circular buffer control circuit of claim 5 , wherein the stride value is programmable.
7. A digital signal processor, comprising:
a register set; and
means for executing a loop of instructions a specified number of times determined by a loop count value, including
first means for executing a first instruction specified by address bits stored in a first portion of a first register of the register set,
second means for decrementing the loop count value stored in a second register of the register set, and
third means for executing a second instruction specified by address bits stored in a second portion of the first register and a third register of the register set.
8. The digital signal processor of claim 7 , further including means for exiting the loop of instructions when the loop count value equals zero.
9. A digital signal processor, comprising:
a register set; and
control logic that executes a loop of instructions a specified number of times determined by a loop count value, wherein the control logic
executes a first instruction specified by address bits stored in a first portion of a first register of the register set,
decrements the loop count value stored in a second register within of the register set, and
executes a second instruction specified by address bits stored in a second portion of the first register and a third register of the register set.
10. The digital signal processor of claim 9 , wherein the control logic exits the loop of instructions when the loop count value equals zero.