Full scan solution for latched-based design
View Patent ↗A full-scan latch is provided that may be used to incorporate design for test functionality in an integrated circuit. The full-scan latch includes a shadow latch, a multiplexer, and a slave latch. The full-scan latch has a test mode and a normal mode. When in the normal mode, the device operates as a transparent latch, passing a data input to its output. When in test mode, the device is operable to pass scan data down a scan chain and to inject scan data into the data path.
1. An apparatus, comprising:
a chain of components responsive to a first clock; and
a scan cell positioned in the chain, the scan cell including:
a master latch to process data signals in response to a second clock,
a shadow latch to process a scan signal in response to the second clock,
a multiplexer to selectively route output from the master latch and the shadow latch to produce multiplexer output, and
a slave latch to process the multiplexer output in response to the first clock.
2. The apparatus of claim 1 wherein the master latch processes data signals from the chain.
3. The apparatus of claim 1 wherein the shadow latch processes scan signals from the chain.
4. The apparatus of claim 1 wherein the chain includes sequential flip-flops.
5. The apparatus of claim 1 wherein the chain includes combinatorial logic.
6. The apparatus of claim 1 wherein the chain includes dynamic logic.
7. The apparatus of claim 1 wherein the scan cell is operative in a first mode for testing and a second mode for normal operation.
8. The apparatus of claim 7 wherein the first mode is selected with the scan signal.
9. The apparatus of claim 1 wherein the second clock is a buffered version of the first clock.
10. The apparatus of claim 1 wherein the master latch and the shadow latch are transparent on different phases of the second clock.
11. A computer readable medium, comprising executable instructions to:
establish a chain of components responsive to a first clock; and
specify a scan cell positioned in the chain, the scan cell including:
a master latch to process data signals in response to a second clock,
a shadow latch to process a scan signal in response to the second clock,
a multiplexer to selectively route output from the master latch and the shadow latch to produce multiplexer output, and
a slave latch to process the multiplexer output in response to the first clock.
12. The computer readable medium of claim 11 wherein the executable instructions to specify a scan cell include executable instructions to specify a master latch to process data signals from the chain.
13. The computer readable medium of claim 11 wherein the executable instructions to specify a scan cell include executable instructions to specify a shadow latch to process scan signals from the chain.
14. The computer readable medium of claim 11 wherein the executable instructions to establish a chain of components include executable instructions to establish sequential flip-flops.
15. The computer readable medium of claim 11 wherein the executable instructions to establish a chain of components include executable instructions to establish combinatorial logic.
16. The computer readable medium of claim 11 wherein the executable instructions to establish a chain of components include executable instructions to establish dynamic logic.
17. The computer readable medium of claim 11 wherein the executable instructions to specify a scan cell include executable instructions to specify a scan cell operative in a first mode for testing and a second mode for normal operation.
18. The computer readable medium of claim 17 wherein the first mode is selected with the scan signal.
19. The computer readable medium of claim 11 wherein the executable instructions to specify a scan cell include executable instructions to specify the second clock as a buffered version of the first clock.
20. The computer readable medium of claim 11 wherein the executable instructions to specify a scan cell include executable instructions to specify the master latch and the shadow latch as transparent on different phases of the second clock.