Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing
View Patent ↗A logic system for resolving port contentions associated with memory-access requests in data packet routing is provided. The logic system comprises a determination logic for assessing and reporting port status of busy or not busy, a command mechanism for issuing commands contingent on determination results and a staged buffer memory for holding pending requests waiting for permission to access the memory. A single request at the head of the buffer memory is considered for port access whereupon if a port is determined to be busy, the command logic issues appropriate commands to units responsible for downloading packets from the memory and for sending new memory-access requests.
1. In a packet processor having a local packet memory (LPM) for storing packet data during processing, the LPM having a plurality of memory cells, the memory cells accessible by at least one memory access port, a system for managing port contention between at least two controllers that access the memory cells, comprising:
a buffer for queuing write requests to the at least one memory port for a first one of the controllers; and
a logic mechanism associated with the buffer for determining whether a write request from said first one of the controllers is within said buffer and is directed at a first one of the memory cells, and if so, whether a read request exists from a second one of the controllers and is directed at said first one of the memory cells;
wherein, if a read request exists from said second one of the controllers and is directed at said first one of the memory cells while said write request is buffered, said read request is delayed until said write request has completed regardless of when said read request occurs.
2. The system of claim 1 wherein said logic mechanism prevents download of packet data from the LPM before queued write requests to the packet data are completed.
3. The system of claim 1 wherein the LPM comprises a set of individual memory cells, each cell having an access port.
4. The system of claim 3 wherein if the port is busy, the logic mechanism checks the buffer for write requests, and finding a write request, issues a command to temporarily suspend packet downloads from the LPM until all write requests in said buffer are completed.
5. The system of claim 3 wherein packet downloading is managed by a packet management unit (PMU) issuing read requests, and said write requests sent to said buffer are other than read requests from said PMU, said PMU reads and said buffer sharing the same port with said PMU, said PMU reads having priority over reads in said buffer, wherein, for packets having data extensive enough to occupy two or more memory cells, packet data is interleaved among cells, such that consecutive cells are dedicated to different packets, ensuring that port contention is limited to alternate cycles.
6. The system of claim 3 wherein packets are assigned an identifier, and wherein said write requests in said buffer are tagged with said identifier, said logic mechanism issuing commands along with said identifier.
7. In a packet processor having a local packet memory (LPM) for storing packet data during processing, the LPM having a plurality of memory cells accessible by at least one access port, a method for managing contention between at least two controllers that access the memory cells, comprising the steps of:
queuing write requests from a first controller to the port in a buffer; and
determining, by a logic mechanism associated with the buffer, whether a write request from the first one of the controllers is within the buffer and is directed at a first one of the memory cells, and if so;
determining whether a read request exists from a second one of the controllers and is directed at the first one of the memory cells; and
if a read request exists from the second one of the controllers and is directed at the first one of the memory cells while the write request is buffered, delaying the read request until said write request has completed, regardless of when said read request occurs.
8. The method of claim 7 for managing contention between at least two controllers that access memory cells, further comprising:
preventing download of packet data from the LPM before all queued write requests to the data are completed, wherein, in said step of determining whether a write request is within the buffer, the logic mechanism checks the buffer for write requests, and finding a write request, issues a command to temporarily suspend packet downloads from the LPM until the queued write requests in the buffer are completed.
9. The method of claim 8 wherein packet downloading is managed by a packet management unit (PMU) issuing read requests, and write requests sent to the buffer are other than read requests from the PMU.
10. The method of claim 8 further comprising:
assigning an identifier to packets in process; and
tagging requests in the buffer with identifiers; wherein
the logic mechanism issues commands along with the packet identifiers.