System and method to trace high performance multi-issue processors

1. A method for tracing instructions in a multi-issue microprocessor core that supports execution of instructions in a plurality of instruction pipelines and which is capable of issuing a plurality of instructions per cycle, comprising:

placing out-of-order issued instructions received from said plurality of instruction pipelines in program sequence order for execution;

selecting an integer non-negative number n of issued instructions to be graduated on each cycle with the maximum number of instructions graduating per cycle depending on the number of issue slots of said multi-issue microprocessor core; and

for graduating instructions, transmitting trace data for said issued instructions according to the program sequence order.

2. The method of claim 1 , wherein said trace data is transmitted using an interface having a plurality of trace buses with each trace bus having an associated trace bus number, the method further comprising:

for each cycle, assigning to each instruction to be traced out a trace bus such that the relative instruction order of a plurality of graduating instructions may be determined from the associated trace bus numbers of the trace buses of said interface utilized to transmit said trace data.

3. The method of claim 2 , wherein said transmitting trace data further comprises: for each instruction traced out, transmitting data associated with said instruction on the same trace bus used to trace out the instruction.

4. The method of claim 2 , wherein said transmitting trace data further comprises: for each instruction traced out, transmitting data associated with the instruction on the first available trace bus together with data order information for associating data with a particular instruction.

5. The method of claim 2 , further comprising: coordinating transaction end points on the trace buses to be the cycle to facilitate determining program sequence order.

6. The method of claim 1 , wherein said trace data includes program counter information.

7. The method of claim 1 , wherein said trace data includes one or more of load address data, load data, store address, and store data information.

8. The method of claim 1 , wherein said transmitting comprises transmitting an issue tag signal for the instructions to facilitate a determination of whether instructions issued together and on which cycle.

9. The method of claim 1 , wherein a reorder buffer is used to place instructions in program sequence order, said reorder buffer having a graduation cycle for graduating instructions in program order; and wherein transmitting trace data comprises transmitting trace data for said instructions in graduation order for each graduation cycle along with information that enables a determination of program execution of said instructions.

10. In a system having a multi-issue microprocessor core that supports execution of instructions in a plurality of instruction pipelines and which is capable of issuing a plurality of instructions per cycle, a tracing apparatus, comprising:

a reorder buffer to place out-of-order issued instructions received from said plurality of instruction pipelines in program sequence order for execution, said reorder buffer selecting an integer non-negative number n of issued instructions to be graduated on each cycle with the maximum number of instructions graduating per cycle depending on the number of issue slots of said multi-issue microprocessor core;

a trace generation module monitoring said reorder buffer and transmitting trace data for each graduation cycle of the reorder buffer along with information that enables a determination of program execution of said instructions.

11. The system of claim 10 , wherein said trace generation module is configured to assign trace data to a plurality of trace buses such that the relative instruction order of graduating instructions may be determined from associated trace bus numbers of said plurality of trace buses.