IP Library Granted Patent US 7,178,133
Granted Patent B1
US 7,178,133 · App. 09/844,673 · Granted Feb 13, 2007

Trace control based on a characteristic of a processor's operating state

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Quick Facts
Patent No.
US 7,178,133
App. No.
09/844,673
Granted
Feb 13, 2007
Kind
B1
Abstract

A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

Claims (45)

1. A tracing method, comprising:

detecting a processor mode of a processor and an application space identity (ASID) value defining an identity of a task being run on said processor;

receiving control signals defining ASID values and processor modes for which tracing is triggered;

effecting a predefined tracing control based on a logical comparison of a current processor mode and a current ASID value to said control signals, whereby tracing is triggered for selected processor modes and ASID values;

storing trace information in a trace memory with a configurable synchronization period corresponding to the trace memory size;

transmitting to said trace memory synchronization information including processor mode values and ASID values; and

retrieving said trace information and said synchronization information after said task is executed on said processor with post-processing trace regeneration software operative to reconstruct said trace information.

2. The method of claim 1 , wherein an indication of said control input for said current operating state is obtained via a software-settable trace control register.

3. The method of claim 1 , wherein said processor modes comprise a kernel mode, a supervisor mode, a user mode, and a debug mode.

4. The method of claim 3 , wherein said kernel mode, said supervisor mode, said user mode, and said debug mode are based on a MIPS32™ or MIPS64™ architecture specification.

5. The method of claim 1 , wherein said tracing is triggered based on G, ASID, U, K, S, DM, and X controls, wherein said G if asserted, implies that all processes are to be traced, whereas if G is not asserted, trace data is processed for a current ASID value, U, if asserted, enables tracing in user mode, K, if asserted enables tracing in kernel mode, S, if asserted, enables tracing in supervisor mode, DM, if asserted, enable tracing in a debug mode, and X, if asserted, enables tracing for exception and error level conditions, said controls enabling tracing when:

((G is asserted OR (ASID equals a current process application space identity value)) AND

((U is asserted AND said processor is in user mode) OR

(K is asserted AND said processor is in kernel mode) OR

(S is asserted AND said processor is in supervisor mode) OR

(DM is asserted AND said processor is in debug mode) OR

(X is asserted AND (an exception level bit is asserted OR an error level bit is asserted)))).

6. A tracing system, comprising:

a processor core for executing instructions; and

trace generation logic that detects a processor mode of said processor core and an application space identity (ASID) value defining an identity of a task running on said processor, said trace generation logic receiving control signals defining ASID values and processor modes for which tracing is triggered and effecting a predefined tracing control based on a logical comparison of a current processor mode and a current ASID value to said control signals, whereby tracing is triggered for selected processor modes and ASID values;

a trace memory to store trace information and synchronization information including processor mode values and ASID values, wherein the trace memory has a configurable synchronization period corresponding to the trace memory size; and

trace regeneration software to retrieve said trace information and synchronization information after said task is executed on said processor and to perform a post-processing reconstruction of said trace information.

7. The tracing system of claim 6 , wherein said control input is identified via a software-settable control register.

8. The tracing system of claim 6 , wherein said processor modes include a kernel mode, a supervisor mode, a user mode, and a debug mode.

9. The tracing system of claim 8 , wherein said kernel mode, said supervisor mode, said user mode, and said debug mode are based on a MIPS32™ or MIPS64™ architecture specification.

10. The tracing system of claim 6 , wherein said trace generation logic triggers tracing based on G, ASID, U, K, S, DM, and X controls, wherein said G if asserted, implies that all processes are to be traced, whereas if G is not asserted, trace data is processed for a current ASID value, U, if asserted, enables tracing in user mode, K, if asserted enables tracing in kernel mode, S, if asserted enables tracing in supervisor mode, DM, if asserted, enable tracing in a debug mode, and X, if asserted, enables tracing for exception and error level conditions, said controls enabling tracing when:

((G is asserted OR (ASID equals a current process application space identity value)) AND

((U is asserted AND said processor is in user mode) OR

(K is asserted AND said processor is in kernel mode) OR

(S is asserted AND said processor is in supervisor mode) OR

(DM is asserted AND said processor is in debug mode) OR

(X is asserted AND (an exception level bit is asserted OR an error level bit is asserted)))).

11. A computer program product comprising:

computer-readable program code for causing a computer to describe a processor core for executing instructions;

computer-readable program code for causing a computer to describe a trace generation logic that detects a processor mode of said processor core and an application space identity (ASID) value defining an identity of a task running on said processor, said trace generation logic receiving control signals defining ASID values and processor modes for which tracing is triggered and effecting a predefined tracing control based on a logical comparison of a current processor mode and a current ASID value to said control signals, whereby tracing is triggered for selected processor modes and ASID values;

computer-readable code to store trace information and synchronization information including processor mode values and ASID values in a trace memory, wherein the trace memory has a configurable synchronization period corresponding to the trace memory size;

computer-readable code to retrieve said trace information and said synchronization information after said task is executed on said processor and to perform a post-processing reconstruction of said trace information; and

a computer-usable medium configured to store the computer-readable program codes.

12. A method for enabling a computer to generate a tracing system, comprising:

transmitting computer-readable program code to a computer, said computer-readable program code including:

computer-readable program code for causing a computer to describe a processor core for executing instructions;

computer-readable program code for causing a computer to describe a trace generation logic that detects a processor mode of said processor core and an application space identity (ASID) value defining an identity of a task running on said processor, said trace generation logic receiving control signals defining ASID values and processor modes for which tracing is triggered and effecting a predefined tracing control based on a logical comparison of a current processor mode and a current ASID value to said control signals, whereby tracing is triggered for selected processor modes and ASID values;

computer-readable program code to store trace information and synchronization information including processor mode values and ASID values in a trace memory, wherein the trace memory has a configurable synchronization period corresponding to the trace memory size; and

computer-readable program code to retrieve said trace information and said synchronization information after said task is executed on said processor and to perform a post-processing reconstruction of said trace information.

13. The method of claim 12 , wherein computer-readable program code is transmitted to said computer over the Internet.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2014
From: BRIDGE CROSSING, LLC
To: ARM FINANCE OVERSEAS LIMITED
Reel/Frame 033074/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2013
From: MIPS TECHNOLOGIES, INC.
To: BRIDGE CROSSING, LLC
Reel/Frame 030202/0440 →