Extended-precision accumulation of multiplier output
View Patent ↗A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (“MFLHXU”) and an instruction to move the contents of a general-purpose register to a portion of the extended accumulator (“MTLHX”).
1. A multiply unit for use in a microprocessor, the microprocessor having at least one general-purpose register for storing a predetermined number of bits, the multiply unit comprising:
at least one input data path for receiving one or more input operands by the multiply unit;
a multiplier connected to receive the one or more input operands and to perform multiplication using the one or more input operands;
an extended-precision accumulated output data path connected to receive an output of the multiplier and including more bits than the sum of the lengths of the one or more input operands; and
an extended-precision accumulator including an extended register, a high-order register, and a low-order register, wherein data from the extended-precision accumulated output path is stored in the extended-precision accumulator.
2. The multiply unit of claim 1 wherein the multiplier provides a multiply-add operation whereby at least two operands are multiplied and added to the contents of the extended-precision accumulator.
3. The multiply unit of claim 1 wherein the multiplier includes:
an arithmetic multiplier; and
a polynomial multiplier.
4. The multiply unit of claim 3 wherein the arithmetic multiplier is a twos-complement binary arithmetic multiplier and the polynomial multiplier is a polynomial basis arithmetic multiplier.
5. The multiply unit of claim 3 wherein the polynomial multiplier provides a multiply-add operation whereby at least two operands are polynomial-basis multiplied and added to the contents of the extended-precision accumulator.
6. The multiply unit of claim 1 wherein the multiplier includes result logic for selecting which values to load into the extended-precision accumulator.
7. The multiply unit of claim 6 wherein the result logic is a multiplexer.
8. The multiply unit of claim 1 wherein the extended register, the high-order register, and the low-order register each include at least one general-purpose register.
9. The multiply unit of claim 1 wherein the extended register stores 8-bit values, the high-order register stores 32-bit values, and the low-order register stores 32-bit values.
10. The multiply unit of claim 1 wherein the microprocessor includes at least one instruction for manipulating the contents of the extended-precision accumulator.
11. The multiply unit of claim 10 wherein the at least one instruction includes an instruction that moves a value from the extended-precision accumulator into a general-purpose register.
12. The multiply unit of claim 11 wherein the instruction further includes shifting the contents of the extended-precision accumulator.
13. The multiply unit of claim 12 the contents of the extended-precision accumulator are shifted rightward by the size of the value moved to the general-purpose register from the extended-precision accumulator.
14. The multiply unit of claim 10 wherein the at least one instruction includes an instruction that moves a value to the extended-precision accumulator from a general-purpose register.
15. The multiply unit of claim 14 wherein the instruction further includes shifting the contents of the extended-precision accumulator.
16. The multiply unit of claim 15 wherein the contents of the extended-precision accumulator are shifted leftward by the size of the value moved from the general-purpose register to the extended-precision accumulator.
17. In a microprocessor core having at least one general-purpose register, a method for performing arithmetic operations, the method comprising:
fetching an instruction to perform an operation from a data store;
reading one or more registers;
performing the operation using a multiply unit, the multiply unit comprising:
at least one input register for receiving one or more input operands by the multiply unit;
a multiplier connected to receive the one or more input operands and to perform multiplication using the one or more input operands;
an extended-precision accumulated output data path connected to receive an output of the multiplier and including more bits than the sum of the lengths of the one or more input operands; and
an extended-precision accumulator including an extended register, a high-order register, and a low-order register, the extended precision accumulator storing data from the extended-precision accumulated output path.
18. The method of claim 17 further comprising using the multiplier to perform a multiply-add operation by multiplying at least two operands and adding the results of the multiplication to the contents of the extended-precision accumulator.
19. The method of claim 17 wherein the multiplier includes:
an arithmetic multiplier; and
a polynomial multiplier.
20. The method of claim 19 wherein the arithmetic multiplier is a twos-complement binary arithmetic multiplier and the polynomial multiplier is a polynomial basis arithmetic multiplier.
21. The method of claim 19 further comprising using the polynomial multiplier to perform a multiply-add operation by multiplying at least two operands and adding the results of the multiplication to the contents of the extended-precision accumulator.
22. The method of claim 17 wherein the multiplier includes result logic for selecting which values to load into the extended-precision accumulator.
23. The method of claim 22 wherein the result logic is a multiplexer.
24. The method of claim 17 wherein the extended register, the high-order register, and the low-order register each include at least one general-purpose register.
25. The method of claim 17 wherein the extended register stores 8-bit values, the high-order register stores 32-bit values, and the low-order register stores 32-bit values.
26. The method of claim 17 further comprising manipulating the contents of the extended-precision accumulator.
27. The method of claim 26 wherein manipulating the contents comprises moving a value from the extended-precision accumulator into a general-purpose register.
28. The method of claim 27 wherein manipulating the contents further includes shifting the contents of the extended-precision accumulator.
29. The method of claim 28 wherein shifting the contents includes shifting the contents of the extended-precision accumulator rightward by the size of the value moved to the general-purpose register from the extended-precision accumulator.
30. The method of claim 26 wherein manipulating the contents includes moving a value to the extended-precision accumulator from a general-purpose register.
31. The method of claim 30 wherein manipulating the contents further includes shifting the contents of the extended-precision accumulator.
32. The method of claim 31 wherein shifting the contents includes shifting the contents of the extended-precision accumulator leftward by the size of the value moved from the general-purpose register to the extended-precision accumulator.
33. A computer-readable medium comprising a microprocessor core embodied in software, the microprocessor core including at least one general-purpose register and a multiply unit, the multiply unit comprising:
at least one input data path for receiving one or more input operands by the multiply unit;
a multiplier connected to receive the one or more input operands and to perform multiplication using the one or more input operands;
an extended-precision accumulated output data path connected to receive an output of the multiplier and including more bits than the sum of the lengths of the one or more input operands; and
an extended-precision accumulator wherein data from the extended-precision accumulated output path is stored in the extended-precision accumulator and the microprocessor core includes an instruction that moves a value from the extended-precision accumulator into a general-purpose register.
34. The computer-readable medium of claim 33 wherein the multiplier provides a multiply-add operation whereby at least two operands are multiplied and added to the contents of the extended-precision accumulator.
35. The computer-readable medium of claim 33 wherein the multiplier includes:
an arithmetic multiplier; and
a polynomial multiplier.
36. The computer-readable medium of claim 35 wherein the arithmetic multiplier is a twos-complement binary arithmetic multiplier and the polynomial multiplier is a polynomial basis arithmetic multiplier.
37. The computer-readable medium of claim 35 wherein the polynomial multiplier provides a multiply-add operation whereby at least two operands are polynomial-basis multiplied and added to the contents of the extended-precision accumulator.
38. The computer-readable medium of claim 33 wherein the multiplier includes result logic for selecting which values to load into the extended-precision accumulator.
39. The computer-readable medium of claim 38 wherein the result logic is a multiplexer.
40. The computer-readable medium of claim 33 wherein the extended-precision accumulator includes:
an extended register;
a high-order register; and
a low-order register.
41. The computer-readable medium of claim 40 wherein the extended register, the high-order register, and the low-order register each include at least one general-purpose register.
42. The computer-readable medium of medium of claim 40 wherein the extended register stores 8-bit values, the high-order register stores 32-bit values, and the low-order register stores 32-bit values.
43. The computer-readable medium of claim 33 wherein the microprocessor core includes at least one instruction for manipulating the contents of the extended-precision accumulator.
44. The computer-readable medium of claim 33 wherein the instruction further includes shifting the contents of the extended-precision accumulator.
45. The computer-readable medium of claim 44 wherein the contents of the extended-precision accumulator are shifted rightward by the size of the value moved to the general-purpose register from the extended-precision accumulator.
46. The computer-readable medium of claim 43 wherein the at least one instruction includes an instruction that moves a value to the extended-precision accumulator from a general-purpose register.
47. The computer-readable medium of claim 46 wherein the instruction further includes shifting the contents of the extended-precision accumulator.
48. The computer-readable medium of claim 47 wherein the contents of the extended-precision accumulator are shifted leftward by the size of the value moved from the general-purpose register to the extended-precision accumulator.